公开(公告)号：DE1815078A1

公开(公告)日：1969-08-28

申请号：DE1815078

申请日：1968-12-17

Applicant: IBM

Inventor： JUN HUMBERTO CORDERO ,  G DRIMAK EDWARD ,  J HUTCHINSON RICHARD ,  F SCHANGHENCY MICHAEL ,  M SHIMP EVERETT

IPC: G06F9/22 ,  G06F9/34 ,  G06F12/04 ,  G06F13/10 ,  G06F13/34 ,  G06F15/78 ,  G06F

Abstract: 1,242,437. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 9 Dec., 1968 [2 Jan., 1968]. No. 58364/68. Heading G4A. A data processing system comprises an addressable main store for storing (microprogramme) control words and other words (e.g. instructions and operands), a control register to which a control word is transferred from the main store in order to control a normal processing routine, a control word generating device responsive to a signal requesting an interrupt processing routine to generate a control word for the interrupt processing routine without reference to the main store and to place the generated control word in the control register, and an auxiliary store accessed by the generated control word to obtain the main store address concerned with the interrupt routine. An addressable local store (the auxiliary store) has locations for operands, main store addresses, indicators, counters and backup, and is addressed from logic controlled by the control register and a mode register (itself controlled by the control register). Interrupt (trap) requests (e.g. from I/O devices or error detectors) are decoded in conjunction with the contents of an MMSK register to select a main store address corresponding to the highest priority request (except that hogging of the interrupt facilities by high priority interrupt sources is prevented), the control word at this address setting a selected bit in the MMSK register. This register now overrides the mode register in the control of local store addressing. Three latches switched on in succession control logic to form and insert into the control register successive control words to control processing of the interrupt, including in the ease of I/O, accessing and updating of a main store address and a count (both from the local store) and data transfer between the main store address and the I/O device involved. Hardware is provided for insertion or deletion of word marks and group mark word marks, if the main store uses them but the I/O devices do not. The programmer may block out certain priority levels in the interrupt selection by microprogramme control of the MMSK register to insert a particular bit into it. When the interrupt has been dealt with, the interrupted microprogramme continues, main store address registers not altered during interrupt processing still holding the next address for the interrupted microprogramme.