公开(公告)号：CA1291577C

公开(公告)日：1991-10-29

申请号：CA601596

申请日：1989-06-08

Applicant: IBM

Inventor： JAMBOTKAR CHAKRAPANI G

IPC: H01L29/73 ,  H01L21/331 ,  H01L27/06 ,  H01L27/082 ,  H01L27/10 ,  H01L27/102 ,  H01L29/205 ,  H01L29/737

Abstract: A compact complementary transistor switch (CTS) memory cell structure utilizing both vertical PNP and vertical NPN transistors in gallium arsenide technology is described. The base region of the vertical PNP transistor merges with the collector region of the vertical NPN transistor. The collector region of the vertical PNP transistor merges with the base region of the vertical NPN transistor. The emitter of the vertical PNP transistor is at the top, and the emitter of the vertical NPN transistor is at the bottom in relation to the emitter of the vertical PNP transistor. This structure leads to improvements in memory density, performance and wireability of a memory array comprising many such cells. A novel yet simple process for making such compact CTS memory cells is also disclosed. FI9-87-018

公开(公告)号：CA1088215A

公开(公告)日：1980-10-21

申请号：CA287343

申请日：1977-09-23

Applicant: IBM

Inventor： JAMBOTKAR CHAKRAPANI G

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/76 ,  B01J17/00

Abstract: FABRICATION OF POWER FIELD EFFECT TRANSISTORS AND THE RESULTING STRUCTURES The fabrication method provides a power metaloxide-semiconductor field-effect transistor (MOSFET) having high switching speed capabilities. The high switching speed is facilitated by narrow channel length which is defined by the difference in lateral diffusion junctions of the P substrate and N source diffusions. The high current capability is produced by the large channel width. The high voltage capability is caused by the use of FET substrate P diffusions designed to be located apart from one another by very small distances. Unbiased or floating P diffusions are designed to flank the outer peripheries of P substrate diffusions. The close proximity of the adjacent P substrate diffusions reduces the electric field in the curvature portion of the P diffusion junctions in the N- silicon body at their inner peripheries, while the presence of the unbiased P diffusions at the appropriate distance from the outer peripheries of P substrate diffusions reduces the electric field in the curvature region of the P substrate diffusions at their outer peripheries. The N silicon body forms the drain region.

公开(公告)号：FR2357035A1

公开(公告)日：1978-01-27

申请号：FR7717614

申请日：1977-06-02

Applicant: IBM

Inventor： JAMBOTKAR CHAKRAPANI G

IPC: H01L29/762 ,  G11C19/28 ,  H01L21/339 ,  H01L27/148 ,  H01L29/10 ,  H01L29/768 ,  G11C11/34

Abstract: A semiconductor integrated charge coupled device is disclosed having an optimized minimum bit length for two-phase operation. Minimum spacing between created depletion regions and electrodes is obtained by having different ion implanted doping levels in the structure in correlation to overlying phase electrodes.

公开(公告)号：CA1286800C

公开(公告)日：1991-07-23

申请号：CA602548

申请日：1989-06-12

Applicant: IBM

Inventor： JAMBOTKAR CHAKRAPANI G

IPC: H01L29/73 ,  H01L21/28 ,  H01L21/331 ,  H01L29/08 ,  H01L29/205 ,  H01L29/737 ,  H01L29/70

Abstract: Heterojunction bipolar transistor technology employing in a body wherein a larger area base electrode over a buried electrode has above it a smaller area electrode, an overhang capability on the portion of the smaller area electrode that operates to mask the base layer in converting the extrinsic portion to high conductivity and assists lift-off of base contact metal such that the base contact metal is in extremely close proximity to the smaller area electrode.

公开(公告)号：CA1134037A

公开(公告)日：1982-10-19

申请号：CA329363

申请日：1979-06-08

Applicant: IBM

Inventor： JAMBOTKAR CHAKRAPANI G

IPC: G11C27/04 ,  H01L21/339 ,  H01L29/10 ,  H01L29/762 ,  G11C11/40 ,  H01L29/70

Abstract: BIPOLAR DUAL-CHANNEL CHARGE-COUPLED DEVICE A bipolar dual-channel charge-coupled device having a first channel at the surface for storing a first bit stream of minority charge carrier packets and a second channel buried in the bulk for storing a second bit stream of majority charge carrier packets. The two bit streams are transferred along their respective surface and buried channels simultaneously and independently of each other, thereby substantially increasing the bit storage density of the chip.

公开(公告)号：CA1099822A

公开(公告)日：1981-04-21

申请号：CA305585

申请日：1978-06-15

Applicant: IBM

Inventor： JAMBOTKAR CHAKRAPANI G

IPC: H01L23/485 ,  H01L29/08 ,  H01L29/732 ,  H01L29/06 ,  H01L29/72

Abstract: FABRICATING INTEGRATED CIRCUITS INCORPORATING HIGH PERFORMANCE BIPOLAR TRANSISTORS A method and resulting semiconductor device which utilizes a mesa emitter structure in a silicon body. The mesa emitter is formed in the silicon semiconductor body and then passivated on its sidewalls using a suitable dielectric. The base region is formed both under the mesa emitter and adjacent thereto. The emitter-base junction is substantially in one plane and substantially without a sidewall component. Contacts are provided to the emitter and to the base region surrounding the mesa emitter. The resulting structure is such that a base contact can be within a few thousand angstroms of the intrinsic base region.

公开(公告)号：CA1112374A

公开(公告)日：1981-11-10

申请号：CA307067

申请日：1978-07-10

Applicant: IBM

Inventor： JAMBOTKAR CHAKRAPANI G

IPC: H01L21/822 ,  H01L21/033 ,  H01L21/265 ,  H01L21/3215 ,  H01L27/04 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

Abstract: A METHOD FOR FORMING SELF-ALIGNED FIELD EFFECT DEVICE BY ION IMPLANTATION A method is provided for making a field effect transistor which comprises forming a layer of an ion beam making material on the surface of a semiconductor body of one-type conductivity. The layer has at least two adjacent apertures. At least a portion of the masking layer between these apertures and in contact with the semiconductor body surface is made of an electrically insulative material if an isolated gate field effect transistor is desired. Then a beam of ions of opposite-type conductivity is directed at the mask body at an energy and dosage sufficient to form two buried regions of opposite-type conductivity fully enclosed within said one-type body respectively beneath these two apertures. Finally, sufficient heat is applied so that the two buried regions diffuse upward until they extend respectively to the surface of the semiconductor body beneath the two apertures; the masking material must have a melting point above the temperature of the diffusion step.

公开(公告)号：CA1106062A

公开(公告)日：1981-07-28

申请号：CA281627

申请日：1977-06-29

Applicant: IBM

Inventor： JAMBOTKAR CHAKRAPANI G

IPC: H01L29/762 ,  G11C19/28 ,  H01L21/339 ,  H01L27/148 ,  H01L29/10 ,  H01L29/768 ,  H01L29/76

Abstract: TWO-PHASE CHARGE COUPLED DEVICE STRUCTURE A semiconductor integrated charge coupled device is disclosed having an optimized minimum bit length for two-phase operation. Minimum spacing between created depletion regions and electrodes is obtained by having different ion implanted doping levels in the structure in correlation to overlying phase electrodes. Also disclosed is means for segmenting a charge coupled device channel with provision for sensing of data in each channel segment to increase the speed of transfer of information from the device. Also disclosed is a novel correlation of transfer or control electrodes of a CCD device with a source of phase clock pulses to provide directionality in a single CCD channel.

公开(公告)号：CA1051122A

公开(公告)日：1979-03-20

申请号：CA267943

申请日：1976-12-15

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  JAMBOTKAR CHAKRAPANI G ,  WANG PAUL P

IPC: H01L29/44

Abstract: POWER TRANSISTOR HAVING IMPROVED SECOND BREAKDOWN CAPABILITY A high voltage power transistor of the type that includes emitter, base and collector regions of alternate conductivity types and PN junctions at the interface of the emitter and base regions, and at the interface of the base and collector regions. The improvement being an emitter region having at least a plurality of spaced elongated finger-like portions; a means in the base region to lower the base resistance in the transverse direction, this means located centrally beneath the finger-like portions of the emitter and comprised either of regions of low resistivity located centrally and beneath each of the finger-like portions, or regions of increased base thickness in the vertical direction also located centrally beneath each of the finger-like portions of the emitter.

公开(公告)号：FR2373881A1

公开(公告)日：1978-07-07

申请号：FR7731858

申请日：1977-10-14

Applicant: IBM

Inventor： JAMBOTKAR CHAKRAPANI G

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L21/22

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) having high switching speed capabilities is shown. The high switching speed is facilitated by narrow channel length which is defined by the difference in lateral diffusion junctions of the P substrate and N source diffusions. The high current capability is produced by the large channel width. The high voltage capability is caused by the use of FET substrate P diffusions designed to be located apart from one another by very small distances. Unbiased or floating P diffusions are designed to flank the outer peripheries of P substrate diffusions. The close proximity of the adjacent P substrate diffusions reduces the electric field in the curvature portion of the P diffusion junctions in the N-silicon body at their inner peripheries, while the presence of the unbiased P diffusions at the appropriate distance from the outer peripheries of P substrate diffusions reduces the electric field in the curvature region of the P substrate diffusions at their outer peripheries. The N silicon body forms the drain region.