公开(公告)号：JPH10209407A

公开(公告)日：1998-08-07

申请号：JP715098

申请日：1998-01-19

Applicant: IBM

Inventor： STUART AQUARISTER BURNS JR ,  HUSSEIN IBRAHIM HANAFI ,  WALDEMAR WOLTER KOKON ,  JEFFREY J WELLSIR

IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a high-density mounted array of a vertical semiconductor device and a method of forming the array. SOLUTION: This array has the column of bit lines 220 and the row of word lines 225. The gates of transistors function as the word lines and source regions 215 or drain regions 240 function as the bit lines. Arrays are formed between the source and drain regions, and have also vertical pillars 230 which function as channels. The source regions 215 are formed in a self-alignment system and are positioned under the pillars. The regions 215 under the adjacent bit lines are separated from each other without increasing a cell size and the smallest area of cells can be maintained. As the source regions are separated from each other, even if the cells are formed into either of a volatile memory cell constitution and a nonvolatile memory cell constitution, the individual cells are addressed by directly tunneling and can be written.

公开(公告)号：JPH10209404A

公开(公告)日：1998-08-07

申请号：JP718798

申请日：1998-01-19

Applicant: IBM

Inventor： STUART AQUARISTER BURNS JR ,  HUSSEIN IBRAHIM HANAFI ,  POWERD REO CALTER ,  WALDEMAR WOLTER KOKON ,  JEFFREY J WELLSIR

IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To obtain the high-density mounted array of a vertical semiconductor device having a pillar with a stack capacitor provided thereon and a method of forming the array. SOLUTION: A pillar 230 functions as a transistor channel and is formed between an upper doped region 240 and lower doped regions 405. The regions 405 are formed by self-alignment and are positioned under the pillar 230. This array has a column of bit lines and a row of word lines. The lower doped regions under the adjacent bit lines are separated from each other without increasing a cell size and the smallest area of cells is maintained. A stack capacitor 520 is formed on the pillar 230 and as the area of the array is not increased, this array is suitable to a DRAM application of a gigabit capacity.