公开(公告)号：JPH10209404A

公开(公告)日：1998-08-07

申请号：JP718798

申请日：1998-01-19

Applicant: IBM

Inventor： STUART AQUARISTER BURNS JR ,  HUSSEIN IBRAHIM HANAFI ,  POWERD REO CALTER ,  WALDEMAR WOLTER KOKON ,  JEFFREY J WELLSIR

IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To obtain the high-density mounted array of a vertical semiconductor device having a pillar with a stack capacitor provided thereon and a method of forming the array. SOLUTION: A pillar 230 functions as a transistor channel and is formed between an upper doped region 240 and lower doped regions 405. The regions 405 are formed by self-alignment and are positioned under the pillar 230. This array has a column of bit lines and a row of word lines. The lower doped regions under the adjacent bit lines are separated from each other without increasing a cell size and the smallest area of cells is maintained. A stack capacitor 520 is formed on the pillar 230 and as the area of the array is not increased, this array is suitable to a DRAM application of a gigabit capacity.

公开(公告)号：JPH10256510A

公开(公告)日：1998-09-25

申请号：JP711998

申请日：1998-01-19

Applicant: IBM

Inventor： STUART AQUARISTER BURNS JR ,  HUSSEIN IBRAHIM HANAFI ,  POWERD REO CALTER ,  WALDEMAR WOLTER KOKON ,  JEFFREY J WERSER

IPC: H01L21/8247 ,  H01L21/24 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To obtain a high density mounting array of vertical semiconductor devices having a pillar and a deep trench capacitor and a method for generating it. SOLUTION: A pillar 230 functions as a transistor channel, and is formed between an upper doped region 240 and a lower doped region 405. The region 405 is a self-alignment type, and disposed under the pillar. This array has a column of bit lines 314, and a row of word lines 275. The lower doped regions 405 of all the cells are separated without increasing a size, and maintained in minimum area of the cell. Deep trench capacitors 405, 580, 585 do not increase array area, and hence the array is adapted to DRAM application of gigabits.

公开(公告)号：JPH10209407A

公开(公告)日：1998-08-07

申请号：JP715098

申请日：1998-01-19

Applicant: IBM

Inventor： STUART AQUARISTER BURNS JR ,  HUSSEIN IBRAHIM HANAFI ,  WALDEMAR WOLTER KOKON ,  JEFFREY J WELLSIR

IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a high-density mounted array of a vertical semiconductor device and a method of forming the array. SOLUTION: This array has the column of bit lines 220 and the row of word lines 225. The gates of transistors function as the word lines and source regions 215 or drain regions 240 function as the bit lines. Arrays are formed between the source and drain regions, and have also vertical pillars 230 which function as channels. The source regions 215 are formed in a self-alignment system and are positioned under the pillars. The regions 215 under the adjacent bit lines are separated from each other without increasing a cell size and the smallest area of cells can be maintained. As the source regions are separated from each other, even if the cells are formed into either of a volatile memory cell constitution and a nonvolatile memory cell constitution, the individual cells are addressed by directly tunneling and can be written.

公开(公告)号：SG105493A1

公开(公告)日：2004-08-27

申请号：SG200102115

申请日：1999-02-15

Applicant: IBM

Inventor： DIANE CATHERINE BOYD ,  STUART M BURNS ,  HUSSEIN IBRAHIM HANAFI ,  YUAN TAUR ,  WILLIAM C WILLE

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

公开(公告)号：SG90231A1

公开(公告)日：2002-07-23

申请号：SG200100583

申请日：2001-02-01

Applicant: IBM

Inventor： DIANE CATHERINE BOYD ,  HUSSEIN IBRAHIM HANAFI ,  MEIKEI LEONG ,  WESLEY CHARLES NATZLE

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/mum or below) and a channel length (sub-lithographic, e.g., 0.1 mum or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.