公开(公告)号：JP2002009286A

公开(公告)日：2002-01-11

申请号：JP2001151973

申请日：2001-05-22

Applicant: IBM

Inventor： JEFFREY W SLATE ,  ANDRES BRIANT ,  EDWARD J NOWAKU

IPC: H01L29/786 ,  H01L21/84

Abstract: PROBLEM TO BE SOLVED: To provide an SOI FET(field effect transistor) integrated circuit having an intentionally introduced parasitic FET between a body and the source of a main transistor. SOLUTION: This is an SOI NFET which regulates automatically high voltage operation by the introduction of a body tie activated in response to the voltage of the body. The body tie is activated by a parasitic FET having a body of a main transistor as a source, body being the lower side part of the main transistor, a drain short-circuited to the source of the main transistor, and a gate being an SOI substrate (having an embedded oxide layer as a gate oxide). Thus, the performance is not disadvantageous at low voltages, and a chip area is scarcely consumed.