公开(公告)号：JP2006093694A

公开(公告)日：2006-04-06

申请号：JP2005257269

申请日：2005-09-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HANAFI HUSSEIN I ,  EDWARD J NOWAKU

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/105 ,  H01L29/0653 ,  H01L29/66628 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a novel structure in a semiconductor device to eliminate or reduce leakage current and junction capacitance. SOLUTION: A structure of a semiconductor device and method of fabricating the same is disclosed. The semiconductor structure includes first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and buried barrier regions disposed between the buried well region and the first source/drain region and disposed between the buried well region and the second source/drain region, wherein the buried barrier regions are adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region, and current leakage and dopant diffusion between the buried well region and the second source/drain region. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供半导体器件中的新颖结构以消除或减少漏电流和结电容。 解决方案：公开了半导体器件的结构及其制造方法。 半导体结构包括第一和第二源极/漏极区域; 设置在所述第一和第二源极/漏极区之间的沟道区; 与通道区域物理接触的掩埋阱区域; 以及埋置的阻挡区域，其设置在所述掩埋阱区域和所述第一源极/漏极区域之间并且设置在所述掩埋阱区域和所述第二源极/漏极区域之间，其中所述掩埋阻挡区域适于防止所述掩埋阱之间的电流泄漏和掺杂剂扩散 区域和第一源极/漏极区域，以及掩埋阱区域和第二源极/漏极区域之间的电流泄漏和掺杂剂扩散。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005303304A

公开(公告)日：2005-10-27

申请号：JP2005112404

申请日：2005-04-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KERRY BERNSTEIN ,  EDWARD J NOWAKU ,  RAINEY BETHANN

IPC: H01L27/08 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/04 ,  H01L29/772 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a drive strength tunable FinFET, and a method of drive strength tuning the FinFET.
SOLUTION: The FinFET has either at least one perpendicular fin 125 and at least one angled fin 130 or has at least one double-gated fin and at least one split-gated fin. The drive strength of the FinFET is tuned by the total number of each type of the fin, and the angle of the angled fin 130 with the perpendicular fin 125.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供驱动强度可调谐FinFET，以及FinFET的驱动强度调谐方法。 解决方案：FinFET具有至少一个垂直翅片125和至少一个成角度的翅片130或具有至少一个双门控翅片和至少一个分裂门控翅片。 FinFET的驱动强度由每种类型的翅片的总数以及倾斜翅片130与垂直翅片125的角度来调节。版权所有：（C）2006，JPO＆NCIPI

公开(公告)号：JP2000150784A

公开(公告)日：2000-05-30

申请号：JP33913499

申请日：1999-11-30

Applicant: IBM

Inventor： EDWARD J NOWAKU ,  TIAN XIAOWEI ,  MIN H TON

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/8605

Abstract: PROBLEM TO BE SOLVED: To enable a noise-insulated buried resistor to meet the requirement of a low-noise analog design requiring a well controlled ohmic resistor. SOLUTION: In order to insulate a buried resistor from the noise of a substrate, an electric field shield composed of an N-well 14 is formed between the buried resistor and substrate. The buried resistor 11 is formed in a P-well 13 formed in the N-well 14. A shallow trench separating area 12 is extended over the wells 13 and 14 and has an opening forming to expose a prescribed surface area in the well 13, and the resistor area 11 is formed in the area of the well 13 demarcated by the opening.

公开(公告)号：JP2006013114A

公开(公告)日：2006-01-12

申请号：JP2004187616

申请日：2004-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COTTRELL PETER E ,  DENNARD ROBERT H ,  EDWARD J NOWAKU ,  ROHRER NORMAN J

IPC: H01L27/14 ,  G01T1/24 ,  H01L29/74 ,  H01L29/786 ,  H01L31/09

Abstract: PROBLEM TO BE SOLVED: To provide a radiation detector formed by using a silicon-on insulator technology.
SOLUTION: The radiation detector comprises a silicon layer formed on an insulating substrate and having a PNPN structure, and a gate layer formed on the PNPN structure and having a PN gate. Latch-up occurs only in response to incident radiation in the radiation detector. In a second mode, the radiation detector has a silicon-on insulator PNPN diode structure and latch-up occurs only in response to incident radiation in the radiation detector. In a third mode, a silicon-on insulator radiation detector has a silicon layer formed on the insulating substrate, the silicon layer has the PNPN structure and a gate layer formed thereon, the gate layer has a PN gate, and latch-up occurs only in response to incident radiation in the radiation detector.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过使用硅绝缘体技术形成的辐射检测器。 解决方案：辐射检测器包括形成在绝缘衬底上并具有PNPN结构的硅层和形成在PNPN结构上并具有PN栅极的栅极层。 仅在响应于辐射探测器中的入射辐射时发生闩锁。 在第二种模式中，辐射探测器具有硅上绝缘体PNPN二极管结构，并且只在响应于辐射探测器中的入射辐射而发生闩锁。 在第三种模式中，硅绝缘体辐射探测器具有形成在绝缘衬底上的硅层，硅层具有PNPN结构和形成于其上的栅极层，栅极层具有PN栅极，并且仅闩锁发生 响应辐射检测器中的入射辐射。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2003264232A

公开(公告)日：2003-09-19

申请号：JP2003008671

申请日：2003-01-16

Applicant: IBM

Inventor： FRIED DAVID M ,  LEIPOLD WILLIAM C ,  EDWARD J NOWAKU

IPC: G06F17/50 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for generating a set of FinFET shapes. SOLUTION: The position of a gate in an FET layout is detected and a set of FinFET shapes matching the gate is generated. More specifically, the method for generating a set of FinFET shapes comprises a step for detecting the position of a gate in an FET layout, a step for finding the axis of the gate, a step for generating a set of FinFET shapes matching the gate, and a step for elongating the set of FinFET shapes perpendicularly to the gate axis. Furthermore, an FinFET layout can be created by correcting the FET layout to include a set of FinFET shapes. More specifically, the system for generating a set of FinFET shapes comprises a subsystem for detecting the position of a gate in an FET layout, and a subsystem for generating a set of FinFET shapes matching the gate. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH10242389A

公开(公告)日：1998-09-11

申请号：JP2700998

申请日：1998-02-09

Applicant: IBM

Inventor： EDWARD J NOWAKU ,  TEIEN SHAOUEI ,  MIN H TON

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/8605

Abstract: PROBLEM TO BE SOLVED: To provide a noise separation burial resistor that satisfies the requirements of a low-noise analog design requiring a properly controlled ohm resistor. SOLUTION: An electric field shielding is provided between a buried resistor and a substrate to separate the buried resistor from the noise of a substrate by a standard buried resistor layout and a mask sequence with two exceptions. First, the buried resistor is not simply arranged at the region of a P well 13 but arranged at the region of an N well 4. Second, to electrically separate the buried resistor from the N well 14, a boron impregnant is added via the buried resistor mask and the P well 13 is formed inside the N well 14, thus electrically connecting the N well 14 to the noiseless ground. The P well 13 inside the N well 14 is left in floating state.

公开(公告)号：JP2005317978A

公开(公告)日：2005-11-10

申请号：JP2005131256

申请日：2005-04-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRYANT ANDRES ,  OMER H DOKUMACI ,  HANAFI HUSSEIN I ,  EDWARD J NOWAKU

IPC: H01L21/265 ,  H01L21/00 ,  H01L21/335 ,  H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42368 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/7856

Abstract: PROBLEM TO BE SOLVED: To provide a method to generate a FinFET with a back gate, which has dielectric layers whose thicknesses are different on its front gate side and back gate side.
SOLUTION: Several steps are included to introduce impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. Impurities that can be introduced through implantation may enhance or retard dielectric formation.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种产生具有背栅的FinFET的方法，其具有在其前栅极侧和后栅极侧的厚度不同的电介质层。 解决方案：包括几个步骤以将杂质引入FinFET的鳍的至少一侧，以形成具有不同厚度的电介质层。 可以通过植入引入的杂质可以增强或延缓电介质形成。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005260240A

公开(公告)日：2005-09-22

申请号：JP2005066896

申请日：2005-03-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDWARD J NOWAKU

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/76 ,  H01L21/82 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L27/1207 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a high-performance CMOS SOI device on a hybrid crystal orientation substrate. SOLUTION: An integrated circuit structure provided with a substrate having at least two types of crystal orientation is disclosed. The first type of transistor is located on the first part of the substrate having an crystal orientation of the first type, and the second type of transistor is located on the second part of the substrate having an crystal orientation of the second type. There is a distortion generating layer on the transistors of the first and second types. Further, the distortion generating layer can distort on the first type of transistor, and get eased up on the second type of transistor. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：在混合晶体取向基板上提供高性能CMOS SOI器件。 公开了具有至少两种晶体取向的基板的集成电路结构。 第一类型的晶体管位于具有第一类型的晶体取向的衬底的第一部分上，并且第二类型的晶体管位于具有第二类型的晶体取向的衬底的第二部分上。 在第一和第二类型的晶体管上存在失真产生层。 此外，失真产生层可以在第一类型的晶体管上发生畸变，并且在第二类晶体管上被放大。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004088101A

公开(公告)日：2004-03-18

申请号：JP2003287197

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  FRIED DAVID M ,  GAUTHIER JR ROBERT J ,  EDWARD J NOWAKU ,  RANKIN JED H ,  TONTI WILLIAM R

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

Abstract: PROBLEM TO BE SOLVED: To provide an improved manufacturing method of an integrated circuit which is made by incorporating both a FinFET and a thick-body device into a single chip. SOLUTION: This manufacturing method of a microelectronic circuit which is made by incorporating both a fin-type field-effect transistor (FinFET) 1801 and a thick-body device 1802 into a single chip can attain an efficiency higher than that of the conventional methods by utilizing common masks and processes. Reduction in the numbers of masks and processes is achieved by utilizing common masks and processes together with several reduction strategies. For example, a structure which usually accompanies a FinFET is formed on a side surface of a thick silicon mesa. A bulk of the silicon mesa is doped to connect to a body contact formed on the opposite side surface of the mesa. This invention also includes the FinFET, thick-body device, and a chip manufactured by the methods associated with the invention. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003318286A

公开(公告)日：2003-11-07

申请号：JP2003107565

申请日：2003-04-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： FRIED DAVID M ,  EDWARD J NOWAKU ,  RAINEY BETH ANN

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/84 ,  H01L27/02 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L31/0328

CPC classification number: H01L27/10838 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell, and its fabricating method, in which cell density can be increased without increasing the fabrication cost or the complicacy excessively.
SOLUTION: A fin arrangement forming a memory cell is provided. More concretely, an access transistor is provided by forming a finned field effect transistor (FET) and a storage capacitor is provided by forming a finned capacitor. When the memory cell is formed using a finned FET and a finned capacitor, memory cell density can be increased significantly as compared with the conventional planar capacitor arrangement. Furthermore, a memory cell can be fabricated with significantly lower process cost and complicacy than those of the conventional deep trench capacitor arrangement.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种其中可以增加细胞密度而不增加制造成本或过度复杂的存储单元及其制造方法。 提供形成存储单元的翅片布置。 更具体地，通过形成翅片场效应晶体管（FET）提供存取晶体管，并且通过形成鳍式电容器来提供存储电容器。 当使用有鳍FET和鳍状电容器形成存储单元时，与常规平面电容器布置相比，可以显着提高存储单元密度。 此外，与传统的深沟槽电容器布置相比，可以以显着更低的工艺成本和复杂性制造存储器单元。 版权所有（C）2004，JPO