公开(公告)号：JPH1069797A

公开(公告)日：1998-03-10

申请号：JP18136897

申请日：1997-07-07

Applicant: IBM

Inventor： CREED FRANCIS ANTHONY ,  BEILEY MARK ,  DRAKE CHARLES EDWARD ,  JENKINS PETER JOEL

IPC: G06F12/16 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To provide a memory system having a bit redundant introduction system higher in operating speed and higher in efficiency. SOLUTION: A CAS signal is supplied to a bit decoder 304 through a delay circuit 1, while supplied to a bit redundant logic circuit 310 through a delay circuit 2 having a shorter delay time than that of the delay circuit 1. Also an address signal CAS 2 bypasses a buffer L2, supplied to the bit redundant logic circuit 310 before it is supplied to the bit decoder 304. Thereby, before a data output 306 is generated from a data array 302, introduction data 312 is supplied to an introduction logic circuit 308 from the bit redundant logic circuit 310 and a defective bit is surely replaced.