公开(公告)号：JPH1069797A

公开(公告)日：1998-03-10

申请号：JP18136897

申请日：1997-07-07

Applicant: IBM

Inventor： CREED FRANCIS ANTHONY ,  BEILEY MARK ,  DRAKE CHARLES EDWARD ,  JENKINS PETER JOEL

IPC: G06F12/16 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To provide a memory system having a bit redundant introduction system higher in operating speed and higher in efficiency. SOLUTION: A CAS signal is supplied to a bit decoder 304 through a delay circuit 1, while supplied to a bit redundant logic circuit 310 through a delay circuit 2 having a shorter delay time than that of the delay circuit 1. Also an address signal CAS 2 bypasses a buffer L2, supplied to the bit redundant logic circuit 310 before it is supplied to the bit decoder 304. Thereby, before a data output 306 is generated from a data array 302, introduction data 312 is supplied to an introduction logic circuit 308 from the bit redundant logic circuit 310 and a defective bit is surely replaced.

公开(公告)号：DE69123372D1

公开(公告)日：1997-01-16

申请号：DE69123372

申请日：1991-01-24

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：DE69119258T2

公开(公告)日：1996-11-21

申请号：DE69119258

申请日：1991-01-19

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  YANKOSKY JAMES ANDREW

IPC: G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

Abstract: Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).

公开(公告)号：DE69119258D1

公开(公告)日：1996-06-13

申请号：DE69119258

申请日：1991-01-19

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  KELLEY GORDON ARTHUR ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  YANKOSKY JAMES ANDREW

IPC: G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

Abstract: Low power addressing systems are provided which include a given number of memory segments (26, 28, 30, 32, 34, 38), each having word and bit/sense lines, a given number of decoders (42, 44, 46, 48, 50, 52, 54, 56) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one word line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a first plurality of transmission gate systems (58, 60, 62, 64), each having first (92) and second (94) transmission gates, with each of the gates being coupled to a different one of the decoders (42, 44, 46, 48, 50, 52, 56), a second decoder (66) having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems (58, 60, 62, 64), first control circuits for selectively activating the first (92) and second (94) gates in each of the first plurality of transmission gate systems (58, 60, 62, 64), a third given number of decoders (68, 70, 72, 74, 76, 80, 82) coupled to the given number of memory segments (26, 28, 30, 32, 34, 36, 38) for selecting one bit/sense line in each of the memory segments (26, 28, 30, 32, 34, 36, 38), a second plurality of transmission gate systems (84, 86, 88, 90), each having first (102) and second (104) transmission gates, with each of the gates of the second plurality of transmission gate systems (84, 86, 88, 90) being coupled to a different one of the third given number of decoders (26, 28, 30, 32, 34, 36, 38), and second control circuits for selectively activating the first (102) and second (104) gates of each of the third plurality of transmission gate systems (26, 28, 30, 32, 34, 36, 38).

公开(公告)号：DE69019665D1

公开(公告)日：1995-06-29

申请号：DE69019665

申请日：1990-09-07

Applicant: IBM

Inventor： DRAKE CHARLES EDWARD ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE

IPC: H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948

Abstract: A CMOS integrated circuit for driving capacitance has an input node (10) and an output node (20) and includes a first transistor (14) operatively connected to the input node (10) which is turned "on" and "off" by the input node (10) to supply an output signal to the output node (20) when turned "on". A second transistor (24) is provided, the output of which is connected to the output node (20) when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor (14) prior to the second transistor (24), and to turn on the second transistor (24) if and only if the slew rate of the output signal of the first transistor (14) is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor (14) will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor (24); however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor (14) will cause the second transistor (24) to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

公开(公告)号：AU6232790A

公开(公告)日：1991-04-18

申请号：AU6232790

申请日：1990-09-10

Applicant: IBM

Inventor： DRAKE CHARLES EDWARD ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE

IPC: H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/0175

Abstract: A CMOS integrated circuit for driving capacitance has an input node (10) and an output node (20) and includes a first transistor (14) operatively connected to the input node (10) which is turned "on" and "off" by the input node (10) to supply an output signal to the output node (20) when turned "on". A second transistor (24) is provided, the output of which is connected to the output node (20) when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor (14) prior to the second transistor (24), and to turn on the second transistor (24) if and only if the slew rate of the output signal of the first transistor (14) is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor (14) will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor (24); however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor (14) will cause the second transistor (24) to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

公开(公告)号：SG43875A1

公开(公告)日：1997-11-14

申请号：SG1996003608

申请日：1991-01-24

Applicant: IBM

Inventor： BARTH JOHN EDWARD JR ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C11/401 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：HK62097A

公开(公告)日：1997-05-16

申请号：HK62097

申请日：1997-05-08

Applicant: IBM

Inventor： BARTH JOHN EDWARD JR ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C11/401 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：DE69019665T2

公开(公告)日：1996-01-25

申请号：DE69019665

申请日：1990-09-07

Applicant: IBM

Inventor： DRAKE CHARLES EDWARD ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE

IPC: H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948

Abstract: A CMOS integrated circuit for driving capacitance has an input node (10) and an output node (20) and includes a first transistor (14) operatively connected to the input node (10) which is turned "on" and "off" by the input node (10) to supply an output signal to the output node (20) when turned "on". A second transistor (24) is provided, the output of which is connected to the output node (20) when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor (14) prior to the second transistor (24), and to turn on the second transistor (24) if and only if the slew rate of the output signal of the first transistor (14) is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor (14) will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor (24); however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor (14) will cause the second transistor (24) to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.