PIPELINED CONTROL APPARATUS WITH MULTI-PROCESS ADDRESS STORAGE

    公开(公告)号:CA1180457A

    公开(公告)日:1985-01-02

    申请号:CA397755

    申请日:1982-03-05

    Applicant: IBM

    Abstract: Control apparatus having n time division channels, controls an m-stage data processing pipeline (n> m> l) for performing operations interleaved and overlapped in time relative to n circuit channels. This apparatus contains m serially coupled control modules associated with respective stages of the pipeline and a source of address signals linked to a first module in the series. Each module includes a control memory, an address register for addressing the memory, an output register for latching addressed control words read out from the memory, and means coupled to the output register for controlling the associated stage of the data pipeline. The address registers are serially coupled to form an address pipeline paralleling the data pipeline. A read/write memory supplies addresses associated with the n channels to a first stage in the address pipeline on a time interleaved basis. These addresses are shifted through the address pipeline in parallel with the movement of associated data through the data pipeline. Simultaneously, new addresses associated with channels currently completing a round of service in the data pipelines, are written into the address memory. Each new address is composed selectively from information in an address register, a control memory output register and the data pipeline. In the preferred embodiment each circuit channel has plural sub-channels, or activity levels, to each of which a unique location is dedicated in the address memory. Readout access to such dedicated locations is varied dynamically, for each channel, as a function of control word information and external conditions relating to associated sub-channels. Such variations effect transfers of control between activity levels.

    3.
    发明专利
    未知

    公开(公告)号:DE10118900B4

    公开(公告)日:2008-01-17

    申请号:DE10118900

    申请日:2001-04-18

    Applicant: IBM

    Abstract: Channel-to-channel communications is provided by integrating channel-to-channel functionality into one or more communication channels of a computing environment which may include heterogenous computer systems. The one or more channels having the integrated CTC function are non-dedicated channels also capable of conventional channel functionality. Work units at such channels are forwarded to either the CTC function or the channel function based on work unit type. Further, a facility is provided for automatically deciding which of the first channel and the second channel is to provide the CTC function for a CTC connection. Partition-to-partition communication can also be accomplished using the integrated CTC function by establishing an internal logical path between a first logical partition and the CTC function and a second logical path between a second logical partition and the CTC function.

    Channel-to-channel connections
    4.
    发明专利

    公开(公告)号:GB2365730A

    公开(公告)日:2002-02-20

    申请号:GB0110606

    申请日:2001-05-01

    Applicant: IBM

    Abstract: Channel-to-channel communications is provided by integrating channel-to-channel functionality into one or more communication channels of a computing environment which may include heterogeneous computer systems. The one or more channels having the integrated CTC function are non-dedicated channels also capable of conventional channel functionality. Work units at such channels are forwarded to either the CTC function or the channel function based on work unit type. Further, a facility is provided for automatically deciding which of the first channel and the second channel is to provide the CTC function for a CTC connection. Partition-to-partition communication can also be accomplished using the integrated CTC function by establishing an internal logical path between a first logical partition and the CTC function and a second logical path between a second logical partition and the CTC function.

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