公开(公告)号：US3465132A

公开(公告)日：1969-09-02

申请号：US3465132D

申请日：1965-08-23

Applicant: IBM

Inventor： CROCKETT PETER N ,  HACKL FRANK J ,  STAFFORD THOMAS S

IPC: G06F11/10 ,  G06F11/00 ,  G11B13/00

CPC classification number: G06F11/10

公开(公告)号：US3399384A

公开(公告)日：1968-08-27

申请号：US48632665

申请日：1965-09-10

Applicant: IBM

Inventor： CROCKETT PETER N ,  KRYGOWSKI MATTHEW A ,  STAFFORD THOMAS S

IPC: G06F13/10 ,  G06F13/26 ,  G06F13/34

CPC classification number: G06F13/34 ,  G06F13/26

公开(公告)号：CA791883A

公开(公告)日：1968-08-06

申请号：CA791883D

Applicant: IBM

Inventor： STAFFORD THOMAS S ,  KRYGOWSKI MATTHEW A ,  CROCKETT PETER N

公开(公告)号：CA1180457A

公开(公告)日：1985-01-02

申请号：CA397755

申请日：1982-03-05

Applicant: IBM

Inventor： CROCKETT PETER N ,  JEWETT ROBERT P ,  SCRIVER ARTHUR J ,  TUCKER THOMAS A

IPC: G06F9/22 ,  G06F9/28 ,  G06F9/38

Abstract: Control apparatus having n time division channels, controls an m-stage data processing pipeline (n> m> l) for performing operations interleaved and overlapped in time relative to n circuit channels. This apparatus contains m serially coupled control modules associated with respective stages of the pipeline and a source of address signals linked to a first module in the series. Each module includes a control memory, an address register for addressing the memory, an output register for latching addressed control words read out from the memory, and means coupled to the output register for controlling the associated stage of the data pipeline. The address registers are serially coupled to form an address pipeline paralleling the data pipeline. A read/write memory supplies addresses associated with the n channels to a first stage in the address pipeline on a time interleaved basis. These addresses are shifted through the address pipeline in parallel with the movement of associated data through the data pipeline. Simultaneously, new addresses associated with channels currently completing a round of service in the data pipelines, are written into the address memory. Each new address is composed selectively from information in an address register, a control memory output register and the data pipeline. In the preferred embodiment each circuit channel has plural sub-channels, or activity levels, to each of which a unique location is dedicated in the address memory. Readout access to such dedicated locations is varied dynamically, for each channel, as a function of control word information and external conditions relating to associated sub-channels. Such variations effect transfers of control between activity levels.

公开(公告)号：CA794516A

公开(公告)日：1968-09-10

申请号：CA794516D

Applicant: IBM

Inventor： HACKL FRANK J ,  STAFFORD THOMAS S ,  CROCKETT PETER N