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公开(公告)号:JPH07325764A
公开(公告)日:1995-12-12
申请号:JP11161495
申请日:1995-05-10
Applicant: IBM
Inventor: CHIYAARUZU EDOWAADO DOREEKU , JIYON ATOKINSON FUIFUIIRUDO , RICHIYAADO DAGURASU HOIIRAA , BARII JIYOO UORUFUOODO
Abstract: PURPOSE: To provide a means for judging a memory device in which an error beyond the correcting capability of on-chip error correction is generated. CONSTITUTION: In one configuration, a memory device using device level error correction traces the situation of error correction related with whether or not the error correction is in an active state or an inactive state, whether or not correction invalidating error beyond the capability of the device level correction is detected, whether or not a recovery option from the correction invalidating error is in the active state, and whether or not the recovery option is reset. In the other configuration, a diagnostic method for judging a situation related with one or plural configurations of the device level error correction used by the memory device is provided. In this diagnostic method, the situation is judged related with one or plural configurations, a flag is set based on this situation, the flag is latched, a diagnostic code is inputted to the memory device, and the latched flag is read.
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公开(公告)号:JPH04222999A
公开(公告)日:1992-08-12
申请号:JP5173291
申请日:1991-03-15
Applicant: IBM
Inventor: JIYON ATOKINSON FUIFUIIRUDO
IPC: G06F11/10 , G06F12/16 , G11C11/401 , G11C29/00 , G11C29/42
Abstract: PURPOSE: To provide an interlock on-chip ECC system for a DRAM restrained to the minimum without compromising a correct ECC operation with degrading of performance due to the on-chip ECC. CONSTITUTION: The effectiveness of data in a certain important stage is ensured with some interlocks used in a system. The residual of the system is allowed to execute on a self reviewing time base so as to make the speed maximum. When data from the DRAM array become effective during taking out operation using e.g. a dummy data line, a signal is transmitted to the ECC, and when data from the ECC is effective during rewriting operation, a signal is transmitted to the DRAM with the same dummy data line.
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公开(公告)号:JPH08316803A
公开(公告)日:1996-11-29
申请号:JP8799196
申请日:1996-04-10
Applicant: IBM
Inventor: MAAKU ADOMAMU BEIRII , JIYON ATOKINSON FUIFUIIRUDO
IPC: H03K5/1532 , H03K5/1534
Abstract: PROBLEM TO BE SOLVED: To generate the identical output pulse width in all input transitions and to generate the delay of only one gate in a circuit by generating an output pulse, at the time of detecting the transition of one node from among several input nodes by using a single delay pass. SOLUTION: A precharging means is provided with plural field effect transistor(FET) devices P0 to P2, which have respective gates connected to respective transition inputs. A 1st charging device FETP 3 charges an output node 25 to a high level. A 2nd charging device FETN3 discharges the output node 25 to a low level. A single delay means is connected between plural transition inputs and the 1st and 2nd charging devices FETP3, FETM3 to turn off the FETP3 and turn on the FETN3. Switching means FETN0 to FETN2 are controlled by plural transition inputs and connected between the output node 25 and the device FETN3, to disconnect the device FETN3 from the output node 25.
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公开(公告)号:JPH02278355A
公开(公告)日:1990-11-14
申请号:JP5682490
申请日:1990-03-09
Applicant: IBM
Inventor: ROBAATO MAACHIN BUREIKU , DAGURASU KUREIGU BOOSEN , CHINNRONGU CHIEN , JIYON ATOKINSON FUIFUIIRUDO , HAWAADO REO KARUTAA
Abstract: PURPOSE: To solve the confrontation which can exist between an error correcting system at a chip level and that at a system level by providing an error correction and detection means at not less than two levels so as to prohibit the operation of an error correction and detection means at a lower-order level when a multiplex fault is generated. CONSTITUTION: A correction impossible error detection signal from the syndrome generator 91 for a chip level error correction circuit 90 is supplied for a latch 55 through an AND gate 53 and an OR gate 56, and the latch 5 supplies a correction prohibiting signal to a decoder 92. The reset input R of he latch 55 receives a reset mode A or B signal generated similarly to a set mode A signal. After a system error circuit is attained, the reset mode A signal resets only he latch 55 through the OR gate 54 to recover normal operation. A set mode B signal is used for executing system judgment by prohibiting on-ship error correction for attaching the memory bit mapping of the position of defective data. Thereby the fault tolerant ability of a high density semiconductor memory is improved.
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公开(公告)号:JPH05173813A
公开(公告)日:1993-07-13
申请号:JP6565492
申请日:1992-03-24
Applicant: IBM
Inventor: KENESU EDOWAADO BEIRUSUTAIN , JIYON ATOKINSON FUIFUIIRUDO , ROURENSU GURIFUISU HERAA , SHINNSAN RII , CHIYAARUZU HENRI SUTATSUPAA
IPC: G01R31/317 , G06F11/08 , G06F11/10 , G06F11/16 , G11C29/00 , H03K19/00 , H03K19/003
Abstract: PURPOSE: To obtain a failure permissible system which does not require any standby unit other than one, operates at a high speed, and can accurately detect failures. CONSTITUTION: Orthogonal outputs (A and A*) are respectively inputted to XOR gates 22 and 24 from a logic block 20 and a standby logic block 20A having the same constitution as that of the block 20 and whether or not the outputs (A and A*) are in an orthogonal state is detected. When the output A of the block 20 is orthogonal, the output A is outputted from a terminal OUT by conducting FETs 36 and 38 and non-conducting FETs 32 and 34. When the output A is not orthogonal, the output A is outputted from the terminal OUT by conducting the FETs 32 and 34. An XOR gate 26 monitors the outputs of the gates 22 and 24 and outputs a flag indicating that only the output of one block is proper and a NOR gate 42 outputs a flag indicating the outputs of both blocks are non-orthogonal so as to indicate whether or not the output from the terminal OUT contains an error.
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公开(公告)号:JPH02294990A
公开(公告)日:1990-12-05
申请号:JP10324590
申请日:1990-04-20
Applicant: IBM
Inventor: JIYON ATOKINSON FUIFUIIRUDO , HAWAADO REO KARUTAA
IPC: G11C11/401 , G11C7/18 , G11C11/4097
Abstract: PURPOSE: To improve the data signal/noise ratio in a high density DRAM by using a non-selective bit line as an AC ground bus and shielding a detected data bit line or a column line. CONSTITUTION: An isolation clock ISOA lowers and turns off an isolation device 1 and 2, at the beginning of an access cycle, in the case of access to a memory cell responding to a word line ML situated on the left side of a sense amplifier 10 on a bit line BL2. With ISOA lowering, a P channel/clamp device 9, 11 turns on, connecting to an array power source potential VD3 a non-active bit line segment BL1 and BL1' separated from the amplifier 10. When a reference word line R2' corresponding to the selected line ML becomes an active state, data and a reference signal are connected to a line segment BL2 and BL2'. Accordingly, signals generating on the reference bit line and the data bit line are all shielded from all dynamic interline connections.
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公开(公告)号:JPS5848295A
公开(公告)日:1983-03-22
申请号:JP11260982
申请日:1982-07-01
Applicant: IBM
IPC: G11C11/404 , G11C11/56 , G11C27/02 , H01L29/78
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公开(公告)号:JPH08328706A
公开(公告)日:1996-12-13
申请号:JP12725796
申请日:1996-05-22
Applicant: IBM
Inventor: JIEFURII SUKOTSUTO TSUINMAAMAN , JIYON ATOKINSON FUIFUIIRUDO , KURISUTOFUAA POORU MIRAA , ROBAATO EDOWAADO BUTSUSHIYU
Abstract: PROBLEM TO BE SOLVED: To provide a dynamic bus system having a central precharging device which uses a control circuit provided with a one-shot generator and a write synchronizing circuit in combination with a logic output module having a pull-up/down device. SOLUTION: The generation of an output enable(OE) signal is interlocked with the turning off of precharge. Therefore, the collision between buses can be avoided, because data are written on a dynamic bus 201 only when a precharging device is inactivated. Because of the resulted circuit, the precharge of the bus 201 is surely performed before the data are written on the bus 201 and, at the same time, a synchronizing OE signal can be generated in the same clock phase as that of a precharge signal.
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公开(公告)号:JPH02278449A
公开(公告)日:1990-11-14
申请号:JP5682790
申请日:1990-03-09
Applicant: IBM
Inventor: ROBAATO MAACHIN BUREIKU , DAGURASU KUREIGU BOOSEN , CHINNRONGU CHIEN , JIYON ATOKINSON FUIFUIIRUDO , HAWAADO REO KARUTAA , TEINNCHIII RO
Abstract: PURPOSE: To improve the total reliability of a memory system by setting at least one output bit from a memory unit related to a correction impossible error to a fixed value at the time of generating the error so as to improve the reproductivity of a hard error. CONSTITUTION: Each of seventy two memory units 10 (chip #1 to #72) supplies a single bit for one system level register 25 and the system level register 25 outputs data through a system level error correction circuit(ECC) 30. When the correction impossible error related with the given chip then, the output of the chip is forcibly made a fixed value. As the result of this, it is certain that system level error display is displayed continually so that a system level error correction and detection circuit is capable of executing correction by complementing or recomplementing for the forced reproducing possibility of the chip error. Thereby the reproductibity of the hard error is improved to improve the total reliability of the memory system.
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公开(公告)号:JPH0212699A
公开(公告)日:1990-01-17
申请号:JP5526189
申请日:1989-03-09
Applicant: IBM
Inventor: JIYON ATOKINSON FUIFUIIRUDO , HAWAADO REO KARUTAA , KURISUTOFUAA POORU MIRAA , SUTEIBUN UIRIAMU TOMASHIYOTSUT
IPC: G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04
Abstract: PURPOSE: To make it possible to obtain word line redundant constitution without the loss of access time by generating a word line drive suppression timing signal when a redundant word line decorder is selected by utilizing the NOR voltage node of a redundant decoder circuit. CONSTITUTION: The output of a drive means is coupled via a filter circuit to a word line drive kill(VWKILL) voltage node. When a signal is impressed on the VWKILL node, the normal word line drive circuit associated with a normal array including that of a reference cell or dummy cell is made completely inoperable. When the redundant word line is selected, a word line drive phase (pulse) is impressed via the redundant word line decoder and a redundant memory cell is selected and further, a redundant memory cell array is physically and directly coupled to the detection side node of the sense amplifier within the sepn. device of a data line or bit line. As a result, the semiconductor memory having the capability of the word line redundancy constitution is obtd. without the loss of the access time.
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