Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor

    公开(公告)号:GB2581945A

    公开(公告)日:2020-09-02

    申请号:GB202009499

    申请日:2018-11-09

    Applicant: IBM

    Abstract: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions. A dependency between the instruction and each of the other instructions is tracked. Instructions are issued from the issue queue based at least in part on the tracking.

    Coalescing global completion table entries in an out-of-order processor

    公开(公告)号:GB2581460B

    公开(公告)日:2021-01-06

    申请号:GB202009111

    申请日:2018-11-09

    Applicant: IBM

    Abstract: Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in-flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.

    Coalescing global completion table entries in an out-of-order processor

    公开(公告)号:GB2581460A

    公开(公告)日:2020-08-19

    申请号:GB202009111

    申请日:2018-11-09

    Applicant: IBM

    Abstract: Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.

    Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor

    公开(公告)号:GB2581945B

    公开(公告)日:2021-01-20

    申请号:GB202009499

    申请日:2018-11-09

    Applicant: IBM

    Abstract: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions. A dependency between the instruction and each of the other instructions is tracked. Instructions are issued from the issue queue based at least in part on the tracking.

    Completing coalesced global completion table entries in an out-of-order processor

    公开(公告)号:GB2581759B

    公开(公告)日:2021-01-20

    申请号:GB202009231

    申请日:2018-11-09

    Applicant: IBM

    Abstract: Aspects of the invention include detecting, in an out-of-order (OoO) processor, that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is the oldest group in an entry of a global completion table (GCT). It is determined that the entry in the GCT is a merged entry that is associated with both the first group of in-flight instructions and a second group of in-flight instructions dispatched immediately subsequent to the first group of in-flight instructions. The first group of in-flight instructions and the second group of in-flight instructions are completed in a single processor cycle. The completing is based at least in part on detecting that all instructions in the first group of in-flight instructions have a status of finished. The completing includes requesting release of resources utilized by both the first and second groups of in-flight instructions.

    Completing coalesced global completion table entries in an out-of-order processor

    公开(公告)号:GB2581759A

    公开(公告)日:2020-08-26

    申请号:GB202009231

    申请日:2018-11-09

    Applicant: IBM

    Abstract: Aspects of the invention include detecting, in an out-of-order (OoO) processor, that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is the oldest group in an entry of a global completion table (GOT). It is determined that the entry in the GOT is a merged entry that is associated with both the first group of in-flight instructions and a second group of in-flight instructions dispatched immediately subsequent to the first group of in-flight instructions. The first group of in-flight instructions and the second group of in-flight instructions are completed in a single processor cycle. The completing is based at least in part on detecting that all instructions in the first group of in-flight instructions have a status of finished. The completing includes requesting release of resources utilized by both the first and second groups of in-flight instructions.

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