公开(公告)号：JPH1092168A

公开(公告)日：1998-04-10

申请号：JP17675597

申请日：1997-07-02

Applicant: IBM

Inventor： JOHANN W NAAGERU ,  MARK W KELLOGG ,  BRUCE G HEEZERUZETSUTO

IPC: G11C5/00 ,  G11C5/14 ,  G11C7/10 ,  H05K1/02

Abstract: PROBLEM TO BE SOLVED: To use a low voltage DRAM on a high voltage memory module by comprising a low voltage regulator and a bus switch. SOLUTION: A 5V-3.3V voltage regulator to be used in combination with a bulk capacitor 16 and a high frequency reduction capacitor is formed to supply an output after the 3.3V regulation to DRAMs 11, 12, 13, 14 through connection with an off-chip 5V power supply. A bus switch 21 receives addresses A0 to A9, write acknowledgment/WE, row address strobe/RAS and column address strobe/CAS as the inputs. Power supplies of the bus switches 21, 22, 23 are connected to the 5V power supply via a diode 25 and the maximum signal amplitude of the 3.3V side is set and maintained to 3.2V. Use of the low voltage DRAMs 11, 12, 13, 14 the high voltage memory module can be realized by comprising a small size voltage regulator 15 and bus switches 21, 22, 23.