公开(公告)号：JPH1092169A

公开(公告)日：1998-04-10

申请号：JP18130297

申请日：1997-07-07

Applicant: IBM

Inventor： BRIAN J CONNOLLY ,  MARK W KELLOGG ,  BRUCE G HEEZERUZETSUTO

IPC: G11C5/00 ,  G06F13/16 ,  G06F13/40 ,  G11C11/401 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To minimize a data line load by providing a bus switch between a system and a RAM and then comprising a logic circuit to produce a signal for enabling this switch into an ASIC. SOLUTION: DRAM chips 301 to 304 and DRAM chips 311 to 314 are connected to a bus switch 309, while DRAM chips 305 to 308 and DRAM chips 315 to 318 are connected to a bus switch 319. A couple of bus switches are connected to ASIC 310 which is connected to a RAS pin and a CAS pin. A data bus load can be minimized by forming a bank DIMM 30 or DIMM 40 by utilizing bus switches 309, 319 or bus switches 409, 419.

公开(公告)号：JPH10283797A

公开(公告)日：1998-10-23

申请号：JP8835198

申请日：1998-04-01

Applicant: IBM

Inventor： MARK W KELLOGG ,  TIMOTHY J DILL ,  ERIC L HEDBERG ,  BERTIN CLAUDE L

IPC: G06F12/16 ,  G06F11/10 ,  G11C7/10 ,  G11C11/401 ,  G11C29/42 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a high-band DRAM which can be used for an error detecting application. SOLUTION: A DRAM array 140 is divided into two or more subarrays 142, 144, 146, and 148. The subarrays are arranged in addressable lines and rows. When the DRAMs are programmed in a normal mode, the burst length becomes '8' and all address spaces of the DRAMs can be utilized for data storage. When the DRAMs are programmed for error detection (ECC mode), the burst length becomes '9' and the array is reconstituted at the part of the array which gives the ninth byte. The address spaces of the DRAMs are reduced by 1/8 in the ECC mode. It is preferable that all nine locations exist on the same page. Each page is divided into eight equal parts. In the normal mode, all of, the eight parts are assigned to the storage of data and, in the FCC mode, seven of the eights parts are assigned to the storage of data and the remaining one part is assigned to the storage of check bits.

公开(公告)号：JP2000030452A

公开(公告)日：2000-01-28

申请号：JP13222499

申请日：1999-05-13

Applicant: IBM

Inventor： DELL TIMOTHY J ,  ERIC L HEDBERG ,  MARK W KELLOGG

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To provide a memory device which stacks some commands, performs internally each command at an appropriate time, and thereby guarantees continuous input/output of data. SOLUTION: A clock counter controls the number of clock cycles to be generated before performing a command by this memory device. This memory device starts access to a memory directly or being delayed by the number of clocks controlled by the clock counter of a command while being controlled by a controller 22. As this memory device is operated as a slave of the controller 22, it cannot perform an instruction in a time other than the time controlled by the controller 22.

公开(公告)号：JPH1092168A

公开(公告)日：1998-04-10

申请号：JP17675597

申请日：1997-07-02

Applicant: IBM

Inventor： JOHANN W NAAGERU ,  MARK W KELLOGG ,  BRUCE G HEEZERUZETSUTO

IPC: G11C5/00 ,  G11C5/14 ,  G11C7/10 ,  H05K1/02

Abstract: PROBLEM TO BE SOLVED: To use a low voltage DRAM on a high voltage memory module by comprising a low voltage regulator and a bus switch. SOLUTION: A 5V-3.3V voltage regulator to be used in combination with a bulk capacitor 16 and a high frequency reduction capacitor is formed to supply an output after the 3.3V regulation to DRAMs 11, 12, 13, 14 through connection with an off-chip 5V power supply. A bus switch 21 receives addresses A0 to A9, write acknowledgment/WE, row address strobe/RAS and column address strobe/CAS as the inputs. Power supplies of the bus switches 21, 22, 23 are connected to the 5V power supply via a diode 25 and the maximum signal amplitude of the 3.3V side is set and maintained to 3.2V. Use of the low voltage DRAMs 11, 12, 13, 14 the high voltage memory module can be realized by comprising a small size voltage regulator 15 and bus switches 21, 22, 23.

公开(公告)号：JP2006048690A

公开(公告)日：2006-02-16

申请号：JP2005220597

申请日：2005-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DELL TIMOTHY J ,  GOWER KEVIN C ,  KARK KEVIN W ,  MARK W KELLOGG ,  MAULE WARREN E

IPC: G06F13/16 ,  G06F12/00

CPC classification number: G06F13/4243 ,  G06F13/1684

Abstract: PROBLEM TO BE SOLVED: To provide a memory system realizing a bus speed multiplier. SOLUTION: This memory system has at least one memory module operating at a data transfer speed of the memory module. The memory system also has a memory controller and at least one memory bus. The memory bus operates at a data transfer speed four times the data transfer speed of the memory module. The memory controller and the memory module are connected to each other by a packet type multitransfer interface via the memory bus. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供实现总线速度倍增器的存储器系统。 解决方案：该存储器系统具有以存储器模块的数据传输速度操作的至少一个存储器模块。 存储器系统还具有存储器控制器和至少一个存储器总线。 存储器总线的数据传输速度是存储器模块的数据传输速度的四倍。 存储器控制器和存储器模块通过存储器总线通过分组类型的多传输接口相互连接。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006048688A

公开(公告)日：2006-02-16

申请号：JP2005220421

申请日：2005-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DELL TIMOTHY J ,  FERRAIOLO FRANK D ,  GOWER KEVIN C ,  KARK KEVIN W ,  MARK W KELLOGG ,  MAULE WARREN E

IPC: G06F12/16

CPC classification number: G06F11/201 ,  G06F11/104

Abstract: PROBLEM TO BE SOLVED: To provide a memory system spared in a segment level. SOLUTION: This memory system includes a cascade type interconnection system spared in the segment level. The cascade type interconnection system has at least two memory assemblies and a memory bus. The memory bus has a plurality of segments, and the memory assemblies are connected to each other via the memory bus. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供在段级别中节省的存储器系统。

解决方案：该存储器系统包括在段级别中节省的级联型互连系统。 级联型互连系统具有至少两个存储器组件和存储器总线。 存储器总线具有多个段，并且存储器组件经由存储器总线相互连接。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2000231534A

公开(公告)日：2000-08-22

申请号：JP2000012794

申请日：2000-01-21

Applicant: IBM

Inventor： DELL TIMOTHY J ,  STEVEN A GRANDON ,  MARK W KELLOGG

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C5/00 ,  G11C7/00 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To obtain a single memory system which can be applied to either a 3.3V DIM or a DDR DIMM by allowing a data storage device to selectively apply each termination to each data inquiry line as necessary. SOLUTION: A DIM identifying circuit means 77 is provided in a memory controller 16b for identifying the kind of a DIMM inserted into a memory 10, and for transmitting a switch activation pulse through a strobe line 78 to termination boards 67 and 68 when it is judged that a DDR DIMM is inserted into the memory 10. The DIMM is provided with an identifying means such as a PROM circuit to be integrated into each DIMM at the time of manufacturing regardless of the kind of the DIMM, that is, 3.3V DIMM or DDR DIMM. Therefore, the kind of the DIMM inserted into the memory 10, that is, 3.3V DIMM or DDR DIMM can be identified by the DIMM identifying circuit means 77.