公开(公告)号：JPH10242856A

公开(公告)日：1998-09-11

申请号：JP1656598

申请日：1998-01-29

Applicant: IBM

Inventor： FRANK DAVID FERRAYORO ,  JOHN EDWIN GERTHBACH ,  CHARLES JOSEPH MASENAS

IPC: H03L7/22 ,  H03L7/07

Abstract: PROBLEM TO BE SOLVED: To provide a phase locked loop system where a technological limit is overcome by providing a capability of selecting an output frequency without interrupting phase locking of an output signal. SOLUTION: The system employs a 1st phase locked loop circuit that is coupled with a 2nd phase locked loop circuit in a way that phases of output signals of them match each other and a switching device that selects an output signal of the 1st phase locked loop or an output signal of the 2nd phase locked loop. The output frequency of this system is switched without interrupting signal phase locking.