公开(公告)号：JPH11330944A

公开(公告)日：1999-11-30

申请号：JP6927499

申请日：1999-03-15

Applicant: IBM

Inventor： COTEUS PAUL W ,  DREPS DANIEL MARK ,  FRANK DAVID FERRAYORO

IPC: H03K5/007 ,  H03K19/0175 ,  H04L25/02

Abstract: PROBLEM TO BE SOLVED: To attain the fast bus pumping by placing a 2nd transistor TR between a 2nd reference voltage and an intermediate node and only the 1st and 2nd inverters connected to each other between the intermediate node and a 1st TR and between the intermediate node and the control input of the 2nd TR respectively. SOLUTION: The inverters 40 and 42 have the switching voltage threshold of about 0.7 VDD and about 0.3 VDD respectively. Therefore, a transistor TR 32 is turned off when the signal voltage level rises up to 0.7 VDD at a terminating node 30. In the same way, a TR 36 is turned on when the signal voltage level dropped down to 0.3 VDD at an intermediate node 30 and then turned off when the signal voltage rises higher than 0.3 VDD. The node 30 is clamped at VSS by the operations of both TR 32 and 36 when a driver 24 drives a signal line 22 at a high logical level.

公开(公告)号：JPH10242856A

公开(公告)日：1998-09-11

申请号：JP1656598

申请日：1998-01-29

Applicant: IBM

Inventor： FRANK DAVID FERRAYORO ,  JOHN EDWIN GERTHBACH ,  CHARLES JOSEPH MASENAS

IPC: H03L7/22 ,  H03L7/07

Abstract: PROBLEM TO BE SOLVED: To provide a phase locked loop system where a technological limit is overcome by providing a capability of selecting an output frequency without interrupting phase locking of an output signal. SOLUTION: The system employs a 1st phase locked loop circuit that is coupled with a 2nd phase locked loop circuit in a way that phases of output signals of them match each other and a switching device that selects an output signal of the 1st phase locked loop or an output signal of the 2nd phase locked loop. The output frequency of this system is switched without interrupting signal phase locking.