公开(公告)号：JP2003303898A

公开(公告)日：2003-10-24

申请号：JP2003078141

申请日：2003-03-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： BERTIN CLAUDE L ,  JOHN JOSEF ELLIS-MONAHAN ,  ERIK RAY HEDBERG ,  HOOK TERENCE B ,  MANDELMAN JACK ALLAN ,  EDWARD JOSEF NOWACK ,  PRICER WILBUR DAVID ,  MIN HO TON ,  TONTI WILLIAM R

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H03K17/06 ,  H03K19/00 ,  H03K19/094 ,  H03K19/0944

CPC classification number: H03K19/0027 ,  H01L29/78606 ,  H03K2217/0018

Abstract: PROBLEM TO BE SOLVED: To provide a switched body SOI CMOS circuit which is provided with an FET element for increasing a FET element threshold voltage.
SOLUTION: A circuit having an SOI element is connected with a body bias voltage, via a switch for selectively connecting a body bias voltage signal with an SOI element body. An NMOS or PMOS SOI element is used as the switched body SOI element. An FET is used as a switch. A gate terminal of the SOI element is connected with an FET element. A gate of the SOI element controls the FET switch connection of the body bias voltage signal to the SOI element, and adjusts a threshold value voltage of the SOI element. A logic circuit including the SOI element and a fabrication process for the SOI element are similarly disclosed.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种开关体SOI CMOS电路，其提供有用于增加FET元件阈值电压的FET元件。 解决方案：具有SOI元件的电路通过用于选择性地将体偏置电压信号与SOI元件体连接的开关与体偏置电压连接。 NMOS或PMOS SOI元件用作开关体SOI元件。 使用FET作为开关。 SOI元件的栅极端子与FET元件连接。 SOI元件的栅极控制体偏置电压信号与SOI元件的FET开关连接，并调整SOI元件的阈值电压。 类似地公开了包括SOI元件的逻辑电路和用于SOI元件的制造工艺。 版权所有（C）2004，JPO

公开(公告)号：JP2007294950A

公开(公告)日：2007-11-08

申请号：JP2007103478

申请日：2007-04-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  JOHN JOSEF ELLIS-MONAHAN ,  GREENE BRIAN J

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/823814

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a transistor device with a dopant depth which is extended and increased so as to have no effect on a channel region of a transistor.
SOLUTION: The method comprises: (a) a step of providing a substrate comprising a semiconductor-on-insulator structure ("SOI") layer separated from a bulk region in the substrate by an embedded dielectric layer; (b) a step of performing a first implantation to the SOI layer in order to attain a predetermined concentration of dopant in an interface of the SOI layer to the embedded dielectric layer; and (c) a step of performing a second implantation to the SOI layer in order to attain a predetermined concentration of dopant in a polycrystalline semiconductor gate conductor ("poly gate") as well as in a source region and a drain region which are arranged to be adjacent to the poly gate. The maximum depth of the first implantation is deeper than the maximum depth of the second implantation.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于形成具有扩展和增加的掺杂剂深度的晶体管器件的方法，以便对晶体管的沟道区域没有影响。 解决方案：该方法包括：（a）提供包括绝缘体上半导体结构（“SOI”）层的衬底的步骤，该衬底通过嵌入的电介质层与衬底中的本体区域分离; （b）为了在SOI层与嵌入介电层的界面中获得预定浓度的掺杂剂，对SOI层进行第一次注入的步骤; 以及（c）为了在多晶半导体栅极导体（“多晶硅”）以及源极区和漏极区中排列的多个半导体栅极导体（“多晶硅”）以及源极区和漏极区域中的掺杂剂浓度达到预定浓度，对SOI层进行第二注入的步骤 与多门相邻。 第一植入的最大深度比第二植入的最大深度更深。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2000332132A

公开(公告)日：2000-11-30

申请号：JP2000116911

申请日：2000-04-18

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  JOHN JOSEF ELLIS-MONAHAN ,  ERIK RAY HEDBERG ,  HOOK TERENCE B ,  MANDELMAN JACK ALLAN ,  EDWARD JOSEF NOWACK ,  PRICER WILBUR DAVID ,  MIN HO TON ,  TONTI WILLIAM R

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H03K17/06 ,  H03K19/00 ,  H03K19/094 ,  H03K19/0944

Abstract: PROBLEM TO BE SOLVED: To increase the threshold voltage of an FET element after switched from a floating state to a biased state by changing a bulk CMOS element to an element within a silicon substrate on an insulator. SOLUTION: A unit cell 1 includes an SOINMOS transistor 60, and its main body or an isolated SOI substrate region 62 is connected to main-body-device transistor switches 64 and 66. The switch 64 is connected to a reference signal 74. When operated by a control signal 80 applied to a gate 78, the switch 64 supplies the signal 74 to the main body 62 of the transistor 60. The main body 62 is connected to a reference signal 76 via a switch 66, and the switch 66 is operated by a control signal 84 supplied to a gate 80. In an active switching state, the threshold voltage level is low, and in a standby state, it is high.