公开(公告)号：JPH10187798A

公开(公告)日：1998-07-21

申请号：JP29374397

申请日：1997-10-27

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  ROBERT P MASREED ,  JOHN S MYUUHIHI

IPC: H01L21/822 ,  G06F12/08 ,  G06F15/78 ,  G06F17/50 ,  G11C5/02 ,  H01L21/82 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for a cache subarray used in microprocessor integrated circuit. SOLUTION: A processor unit is arranged in the center area of a microprocessor integrated circuit, the peripheral area is specified as a cache memory array area, and a specified number of cache memory subarrays are arranged in the peripheral area while surrounding the center area so that a variable-size cache memory array is efficiently arranged. The cache memory subarray includes a part, where one cache word is fixed. The microprocessor integrated circuit itself has a modular cache memory array of variable size, the peripheral area which is specified as the cache memory array area and surrounds the center area, and the specific cache memory subarrays arranged in the peripheral area so as to constitute the cache memory array.