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    ACCESSING METHOD, PROCESSOR AND COMPUTER SYSTEM
    2.
    发明专利
    ACCESSING METHOD, PROCESSOR AND COMPUTER SYSTEM 失效

    公开(公告)号：JPH10254773A

    公开(公告)日：1998-09-25

    申请号：JP3483598

    申请日：1998-02-17

    Applicant: IBM

    Inventor： RAVI KUMER ARIMIRRI ,  JOHN STEPHEN DODSON ,  JERRY DON LEWIS ,  DEREK EDWARD WILLIAMS

    IPC: G06F9/52 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177

    Abstract: PROBLEM TO BE SOLVED: To provide a method for loading/reserving instruction by marking a highest-order cache as a reserved one, sending reserving bus operation from the highest-order cache to a cache at a second level and casting out this value from the highest-order cache after sending. SOLUTION: When a processor first accesses a value to read by the loading and reserving instruction, the value is placed at all the cache levels to the highest-order level cache (30). A corresponding block in the cache is marked as a reserved one (32). After then, the processor executes another instruction (34). When the value is expelled from the highest-order level cache (36), reserving bus operation is sent to a level just under it (38) but sent to only the level just under it. After receiving bus operation is sent to a next low-order level cache, a block is assign-released from the cache at the highest-order level (40).

    Multiprocessor data processing system
    3.
    发明专利
    Multiprocessor data processing system 有权
    多处理器数据处理系统

    公开(公告)号：JP2004326798A

    公开(公告)日：2004-11-18

    申请号：JP2004128785

    申请日：2004-04-23

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： RAVI KUMER ARIMIRRI ,  GUY LYNN GUTHRIE ,  LIVINGSTON KIRK SAMUEL

    IPC: G06F12/10 ,  G06F15/177

    CPC classification number: G06F12/1072 ,  G06F12/1027 ,  G06F2212/682

    Abstract: PROBLEM TO BE SOLVED: To provide a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations (for making a conversion index buffer TLB disabled) from multiple processors within a partition to complete concurrently. SOLUTION: When the TLBI is received and an entry of a master processor in the TLB is disabled, a processor starts the TLBI protocol and it leads TLBI handling similar to a local barrier instruction. A corresponding TLB entry is disabled. In addition, transfer of a fetched instruction for an execution queue is stopped, operation by the execution unit is stopped and a queued instruction in the execution unit queue is deleted. After the queue is completely drained, the TLBI is issued in a state of mutual connection and corresponding entry in a TLB of another snooping processor is disabled. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供实现TLBI协议的对称多处理器数据处理系统（SMP），其实现多个TLBI操作（用于使转换索引缓冲区TLB被禁用）从分区内的多个处理器并发完成。 解决方案：当接收到TLBI并且TLB中的主处理器的条目被禁用时，处理器启动TLBI协议，并且导致类似于本地屏障指令的TLBI处理。 相应的TLB条目被禁用。 此外，停止对执行队列的取出指令的传送，执行单元的操作停止，并且执行单元队列中的排队指令被删除。 队列完全耗尽之后，TLBI被发布为相互连接的状态，另一个侦听处理器的TLB中的相应条目被禁用。 版权所有（C）2005，JPO＆NCIPI

    METHOD AND DEVICE FOR GUARANTEEING CACHE COHERENCY
    4.
    发明专利
    METHOD AND DEVICE FOR GUARANTEEING CACHE COHERENCY 失效

    公开(公告)号：JPH10260899A

    公开(公告)日：1998-09-29

    申请号：JP5108698

    申请日：1998-03-03

    Applicant: IBM

    Inventor： RAVI KUMER ARIMIRRI ,  JOHN STEPHEN DODSON ,  JERRY DON LEWIS

    IPC: G06F12/08

    Abstract: PROBLEM TO BE SOLVED: To provide an improved mechanism for maintaining the cache coherency in a data processing system, by forcedly setting corrected data in an independent data cache to be at a lower order cache hierarchy level. SOLUTION: Processors 102 and 104 contain independent level one instruction caches and level one data caches in the respective processors. The processor 102 contains the instruction cache 106 and the data cache 108 and the processor 104 contains the instruction cache 110 and the data cache 112. Thus, cache coherency is guaranteed in the data processing system using cache hierarchy having the independent instruction caches 106 and 110 and the data caches 108 and 112 in at least one level. Namely, the independent instruction caches 106 and 110 and the data caches 108 and 112 are efficiently made coherent.

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