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    3.
    发明专利
    未知

    公开(公告)号：DE3580396D1

    公开(公告)日：1990-12-13

    申请号：DE3580396

    申请日：1985-04-30

    Applicant: IBM

    Inventor： HESTER PHILIP DOYCE ,  JOHNSON WILLIAM MICHAEL

    IPC: G06F9/30 ,  G06F13/12 ,  G06F13/36 ,  G06F13/38 ,  G06F13/42

    Abstract: The invention is directed to a data processing system having a CPU (10) and at least one external unit acquiring data from or providing data to the CPU (10) and I/O bus (II) for the transfer of data between the CPU (10) and the external unit. The system includes means for controlling register to register data transfers being conducted during time cycles coincident with the transfer of data to or from the external unit. Thus, the register to register data transfer within the CPU (1) are overlapped with the data transfers over the I/O bus (II) to main storage (12). The data transfers to and from main storage (12) are generally considerably longer that the simpler register to register data transfer. The system may be operated so that several register to register transfers may take place during the time required for a transfer of data to or from the external unit.

    4.
    发明专利
    未知

    公开(公告)号：BR8700153A

    公开(公告)日：1987-12-01

    申请号：BR8700153

    申请日：1987-01-15

    Applicant: IBM

    Inventor： JOHNSON WILLIAM MICHAEL

    IPC: G06F12/10 ,  G06F12/08

    Abstract: A method of operating a data processing system using virtual memory in which virtual memory addresses are formed by a base register value and a displacement value and are mapped to real memory addresses includes the steps of adding the base register value content and the displacement value, and simultaneously with the adding operation, performing a translation of the base register value to produce a virtual address corresponding to the base register value.

    5.
    发明专利
    未知

    公开(公告)号：DE3586842T2

    公开(公告)日：1993-06-09

    申请号：DE3586842

    申请日：1985-09-13

    Applicant: IBM

    Inventor： JOHNSON WILLIAM MICHAEL

    IPC: G06F15/16 ,  G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38

    Abstract: A microprogrammed parallel processor including a plurality of subprocessors operates under the control of microinstructions. Each microinstruction contains a plurality of micro-operations each of which requires one or more subprocessors for execution. All micro-operations for which required subprocessors are available are immediately carried out. Any remaining micro-operations within a microinstruction which are not executed due to lack of subprocessor availability are recycled. These remaining micro-operations are executed in subsequent cycles as a required subprocessor becomes available. The entire microinstruction is not recycled but only those portions of it, i.e., the unexecuted micro-operations, are recycled and executed in a subsequent cycle. The microinstruction being executed is stored in a latch until all micro-operations within the microinstruction are executed. At that time, the next microinstruction is fetched into the latch.

    7.
    发明专利
    未知

    公开(公告)号：DE3586842D1

    公开(公告)日：1992-12-24

    申请号：DE3586842

    申请日：1985-09-13

    Applicant: IBM

    Inventor： JOHNSON WILLIAM MICHAEL

    IPC: G06F15/16 ,  G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38

    Abstract: A microprogrammed parallel processor including a plurality of subprocessors operates under the control of microinstructions. Each microinstruction contains a plurality of micro-operations each of which requires one or more subprocessors for execution. All micro-operations for which required subprocessors are available are immediately carried out. Any remaining micro-operations within a microinstruction which are not executed due to lack of subprocessor availability are recycled. These remaining micro-operations are executed in subsequent cycles as a required subprocessor becomes available. The entire microinstruction is not recycled but only those portions of it, i.e., the unexecuted micro-operations, are recycled and executed in a subsequent cycle. The microinstruction being executed is stored in a latch until all micro-operations within the microinstruction are executed. At that time, the next microinstruction is fetched into the latch.

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