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    1.
    发明专利
    未知

    公开(公告)号：DE3585986D1

    公开(公告)日：1992-06-11

    申请号：DE3585986

    申请日：1985-09-24

    Applicant: IBM

    Inventor： WRIGHT CHARLES GORDON

    IPC: G06F1/24 ,  G06F9/445 ,  G06F12/06 ,  G06F13/14 ,  G06F9/44

    Abstract: A plurality of controllers are connected to a common bus (11) in turn connected to a central processor (10). Each of the controllers (18, 19, 19A) respectively serves as an interface between the central processor and at least one storage unit (12, 13) or input/output device (14). In order for the controllers to distinguish between addresses, the addresses sent from the central processor contain identifier segments indicative of the controller to which the address is being sent. Controllers in turn contain programmable comparison means (20, 21, 22) for comparing the identifier segments in addresses to a stored controller identifier indicative of the controller. Because the comparison means are programmable, controller identifiers have to be set up each time the system is turned on. Consequently, the present invention provides such turn on or initialization means including a read-only initialization program stored in one of the storage units: the controller interfacing with this storage unit becomes a master controller; the master controller has apparatus which is selectively activated only during initialization for accepting all addresses irrespective of the identifier segment. The other controllers have apparatus selectively activated only during initialization for disabling the comparison means and such other controllers so that no addresses are accepted by the other controllers during the initialization. In other words, the comparison means in the master controller is completely bypassed during initialization whereby the read-only initialization program is accessed only through the master controller.

    2.
    发明专利
    未知

    公开(公告)号：DE69525093D1

    公开(公告)日：2002-03-14

    申请号：DE69525093

    申请日：1995-03-31

    Applicant: IBM

    Inventor： WRIGHT CHARLES GORDON

    IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10 ,  H03L7/06 ,  H03L7/197 ,  H03L7/099

    Abstract: A method and apparatus are provided for generating a phase-controlled clock signal within a microprocessor. A first clock signal having a first frequency is input. After a reset event, the first clock signal transitions in a first direction at a time t. A second clock signal is output having a second frequency related to the first frequency by a non-integer ratio. The second clock signal transitions in the same direction as the first clock signal at time t.

    4.
    发明专利
    未知

    公开(公告)号：BR9501494A

    公开(公告)日：1997-08-19

    申请号：BR9501494

    申请日：1995-04-07

    Applicant: IBM

    Inventor： WRIGHT CHARLES GORDON

    IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10 ,  H03L7/06 ,  H03L7/197 ,  G06F1/04

    Abstract: A method and apparatus are provided for generating a phase-controlled clock signal within a microprocessor. A first clock signal having a first frequency is input. After a reset event, the first clock signal transitions in a first direction at a time t. A second clock signal is output having a second frequency related to the first frequency by a non-integer ratio. The second clock signal transitions in the same direction as the first clock signal at time t.

    6.
    发明专利
    未知

    公开(公告)号：DE69525093T2

    公开(公告)日：2002-10-17

    申请号：DE69525093

    申请日：1995-03-31

    Applicant: IBM

    Inventor： WRIGHT CHARLES GORDON

    IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10 ,  H03L7/06 ,  H03L7/197 ,  H03L7/099

    Abstract: A method and apparatus are provided for generating a phase-controlled clock signal within a microprocessor. A first clock signal having a first frequency is input. After a reset event, the first clock signal transitions in a first direction at a time t. A second clock signal is output having a second frequency related to the first frequency by a non-integer ratio. The second clock signal transitions in the same direction as the first clock signal at time t.

    8.
    发明专利
    未知

    公开(公告)号：DE3584402D1

    公开(公告)日：1991-11-21

    申请号：DE3584402

    申请日：1985-06-19

    Applicant: IBM

    Inventor： WALDECKER DONALD EMIL ,  WRIGHT CHARLES GORDON

    IPC: G06F13/36 ,  G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F15/16 ,  G06F13/18

    Abstract: A plurality of data processor units (11, 16 17) are connected to a common bus (10) which is connected to first and second interleaved storage units (1, 2). The system is a synchronous one in which timing means (23) establish a series of information transfer intervals (t0-t7, etc.). One or more of the processors units (16, 17) contain apparatus for selectively commencing an address transfer on the bus (10) to one of the storage units (1, 2) during a transfer interval; the storage transaction initiated by the address transfer will require more than the one transfer interval to complete. One or more of the processors (16. 17) have means (3, 4) for monitoring the bus (10) in order to determine whether an address on the bus has been transferred to the first or the second storage unit (1.2) during a particular transfer interval. The address transfer apparatus further includes apparatus (50) responsive to the monitoring apparatus for selectively transferring the next subsequent address to the other of said storage units (1, 2) to thus achieve alternating interleaving between storage units (1, 2).

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