公开(公告)号：SE7804921A

公开(公告)日：1978-11-03

申请号：SE7804921

申请日：1978-04-28

Applicant: IBM

Inventor： JOSHI M L ,  LANDLER P F-J ,  SILVERMAN R

IPC: H01L27/10 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78 ,  H01L27/04

CPC classification number: H01L27/10844 ,  H01L21/768 ,  H01L21/8234

公开(公告)号：SE7806951A

公开(公告)日：1978-12-31

申请号：SE7806951

申请日：1978-06-16

Applicant: IBM

Inventor： JOSHI M L ,  PRICER W D

IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/22

CPC classification number: G11C11/403

公开(公告)号：AU514832B2

公开(公告)日：1981-02-26

申请号：AU3488378

申请日：1978-04-07

Applicant: IBM

Inventor： JOSHI M L ,  PRICER W D

IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C7/06 ,  G11C11/24 ,  G11C11/34

Abstract: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

公开(公告)号：SE7806951L

公开(公告)日：1978-12-31

申请号：SE7806951

申请日：1978-06-16

Applicant: IBM

Inventor： JOSHI M L ,  PRICER W D

IPC: G11C11/403 ,  G11C11/419 ,  G11C11/405 ,  G11C11/42 ,  G11C11/22

Abstract: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

公开(公告)号：SE7804921L

公开(公告)日：1978-11-03

申请号：SE7804921

申请日：1978-04-28

Applicant: IBM

Inventor： JOSHI M L ,  LANDLER P F-J ,  SILVERMAN R

IPC: H01L27/10 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78 ,  H01L27/04