公开(公告)号：SE417381B

公开(公告)日：1981-03-09

申请号：SE7702445

申请日：1977-03-04

Applicant: IBM

Inventor： PRICER W D

IPC: G11C5/02 ,  G11C11/56 ,  G11C11/24 ,  G11C11/34 ,  G11C11/35 ,  H01L27/10 ,  H01L27/108

Abstract: A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The capacitors having the larger voltage store the greater amount of charge. This charge can then be detected by measuring the voltage across the storage capacitors when a work pulse again connects the charge source with each of the capacitors.

公开(公告)号：AU501754B2

公开(公告)日：1979-06-28

申请号：AU2365177

申请日：1977-03-25

Applicant: IBM

Inventor： PRICER W D

IPC: G11C11/56 ,  G11C5/02 ,  G11C11/24 ,  G11C11/34 ,  G11C11/35 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L27/04 ,  H01L23/50 ,  H01L49/00 ,  H01L21/22 ,  H01L21/265 ,  H01L21/82 ,  H01L29/76

Abstract: A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The capacitors having the larger voltage store the greater amount of charge. This charge can then be detected by measuring the voltage across the storage capacitors when a work pulse again connects the charge source with each of the capacitors.

公开(公告)号：BE775348A

公开(公告)日：1972-03-16

申请号：BE775348

申请日：1971-11-16

Applicant: IBM

Inventor： BEAUSOLEIL W F ,  HO I T ,  PRICER W D

IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00 ,  G11C

Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

公开(公告)号：BE759562A

公开(公告)日：1971-04-30

申请号：BE759562D

Applicant: IBM

Inventor： BEAUSOLEIL W F ,  ORDEMANN F A JR ,  PRICER W D ,  VOGL NORBERT G JR

IPC: G11C19/00 ,  G11C19/18 ,  G06F

Abstract: An electronic bulk storage having the characteristics of a sequential access storage device. Data are stored parallel by word in a plurality of electronically rotatable memory elements selectable by a memory selection matrix. Each element has a feed-back loop for recirculating data and when selected, a group of elements at an address N is read in parallel a word at a time by electronically rotating data bits stored in the selected memory elements at an address. Controls are provided to select memory elements N+1 whenever elements at address N are selected by the selection matrix. First data is read out of the elements at address N and then data is read out of the elements at address N+1 without any time lost for reselection of memory elements.

公开(公告)号：SE383428B

公开(公告)日：1976-03-08

申请号：SE1502471

申请日：1971-11-24

Applicant: IBM

Inventor： BEAUSOLEIL W F ,  HO I T ,  JEN T-S ,  PRICER W D

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  H01L23/535 ,  H01L27/10 ,  G11C11/40

公开(公告)号：SE383427B

公开(公告)日：1976-03-08

申请号：SE1638071

申请日：1971-12-21

Applicant: IBM

Inventor： BEAUSOLEIL W F ,  HO I T ,  PRICER W D

IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00 ,  G11C9/06

Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

公开(公告)号：SE7806951A

公开(公告)日：1978-12-31

申请号：SE7806951

申请日：1978-06-16

Applicant: IBM

Inventor： JOSHI M L ,  PRICER W D

IPC: G11C11/419 ,  G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/22

CPC classification number: G11C11/403

公开(公告)号：CA921158A

公开(公告)日：1973-02-13

申请号：CA68270

申请日：1969-11-25

Applicant: IBM

Inventor： PRICER W D ,  BEAUSOLEIL W F

IPC: G06F13/40

公开(公告)号：BE773703A

公开(公告)日：1972-01-31

申请号：BE773703

申请日：1971-10-08

Applicant: IBM

Inventor： BEAUSOLEIL W F ,  HO I T ,  JEN T-S ,  PRICER W D

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  H01L23/535 ,  H01L27/10 ,  G11C

公开(公告)号：AU6753981A

公开(公告)日：1981-09-10

申请号：AU6753981

申请日：1981-02-23

Applicant: IBM

Inventor： PRICER W D ,  SELLECK J E

IPC: G11C17/00 ,  G11C11/34 ,  G11C11/40 ,  G11C11/56 ,  G11C17/12 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/112 ,  H01L29/10

Abstract: A storage system, such as a read only memory, is provided which includes field effect transistors (54, 56) each having first and second spaced apart diffusion regions (38,40; 46, 48) of a given conductivity and a gate electrode (28,30), with at least one of the two diffusion regions of selected transistors having a third diffusion (42,44) adjacent to one of the first and second diffusion regions (38, 40; 46,48) under the gate electrodes (28, 30) to provide a higher voltage threshold for the gate electrode to one diffusion than for the gate electrode to the other of the two diffusions. A voltage is applied to the first diffusion (38) having a polarity and magnitude sufficient to neutralize or eliminate the effects of the higher threshold during a first time period and the current flowing between the first and second diffusions (38,40; 46,48) is sensed. During a second period of time the voltage is applied to the second diffusion (46, 48) and the current flow between the first and second diffusions (38, 40; 46, 48) is again sensed. In this manner two cells or bits of information are stored in each transistor (54, 56), one at the first diffusion (38) and one at the second diffusion (48). Multilevel storing may also be employed by establishing one of more than two predetermined voltage thresholds at each of the first and second diffusions.