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公开(公告)号：DE3809831A1
公开(公告)日：1988-10-06
申请号：DE3809831
申请日：1988-03-23
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , JACKSON KEVIN MICHAEL , JUDICE DARRYL EDMOND , PESTONJI HOSHANG RATAN
Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.
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公开(公告)号：DE69024912D1
公开(公告)日：1996-02-29
申请号：DE69024912
申请日：1990-10-17
Applicant: IBM
Inventor： JUDICE DARRYL EDMOND
IPC: G06F13/362
Abstract: A logic controlled delay circuit (305) is connected into the arbitration logic (155) of a computer system of the type having a main data bus (115) which is subject to control by multiple masters (140). The delay is so programmed that the default master, which is the main processor (CPU) (100) for the system and is assigned the residual or default priority, is assured a predefined portion of the time available on the bus (115). By so inserting and controlling the delay that the "hold" signal to the CPU (100) is delayed whenever the CPU (100) is granted access to the bus (115) , other devices, are unable to seize the bus (115) until the delay has ended at which time the CPU (100) is triggered by the delayed signal to respond with an acknowledge which serves to permit arbitration to begin. By this technique a standard microprocessor such as an Intel 80386 can operate in such an architecture without being preempted from the bus (115) by the higher priority devices (140) to an extent that system operation deteriorates.
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公开(公告)号：PH24865A
公开(公告)日：1990-12-26
申请号：PH36463
申请日：1985-02-05
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , JACKSON KEVIN MICHAEL , JUDICE DARRYL EDMOND , PESTONJI HOSHANG RATAN
Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.
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公开(公告)号：IT1216131B
公开(公告)日：1990-02-22
申请号：IT1982688
申请日：1988-03-18
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , JACKSON KEVIN MICHAEL , JUDICE DARRYL EDMOND , PESTONJI HOSHANG RATAN
Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.
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公开(公告)号：BE1001065A3
公开(公告)日：1989-06-27
申请号：BE8701347
申请日：1987-11-26
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , JACKSON KEVIN MICHAEL , JUDICE DARRYL EDMOND , PESTONJI
Abstract: Dispositif d'ordinateur personnel comportant une unité de commande d'interruption associée et qui est de préférence conçu pour fonctionner avec des programmes et répondre à des signaux de commande relatifs aux interruptions dans un mode tel que le mode sensible aux niveaux, mais comporte des circuits qui permettent au système de convertir et de répondre à des signaux de commande de logiciel relatifs à des interruptions dans un autre mode tel que le mode sensible aux fronts, le système, dans ce cas, traitant les signaux en mode sensible aux fronts exactement comme s'il s'agissait de signaux en mode sensible aux niveaux.
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Patent Agency Ranking
公开(公告)号：GB2202658B
公开(公告)日：1991-07-31
申请号：GB8728925
申请日：1987-12-10
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , JACKSON KEVIN MICHAEL , JUDICE DARRYL EDMOND , PESTONJI HOSHANG RATAN
Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.
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公开(公告)号：FR2613097A1
公开(公告)日：1988-09-30
申请号：FR8716749
申请日：1987-11-27
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , JUDICE DARRYL EDMOND , JACKSON KEVIN MICHAEL , PESTONJI HOSHANG RATAN
Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.
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公开(公告)号：IT8819826D0
公开(公告)日：1988-03-18
申请号：IT1982688
申请日：1988-03-18
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , JACKSON KEVIN MICHAEL , JUDICE DARRYL EDMOND , PESTONJI HOSHANG RATAN
Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.
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公开(公告)号：DE69024912T2
公开(公告)日：1996-08-08
申请号：DE69024912
申请日：1990-10-17
Applicant: IBM
Inventor： JUDICE DARRYL EDMOND
IPC: G06F13/362
Abstract: A logic controlled delay circuit (305) is connected into the arbitration logic (155) of a computer system of the type having a main data bus (115) which is subject to control by multiple masters (140). The delay is so programmed that the default master, which is the main processor (CPU) (100) for the system and is assigned the residual or default priority, is assured a predefined portion of the time available on the bus (115). By so inserting and controlling the delay that the "hold" signal to the CPU (100) is delayed whenever the CPU (100) is granted access to the bus (115) , other devices, are unable to seize the bus (115) until the delay has ended at which time the CPU (100) is triggered by the delayed signal to respond with an acknowledge which serves to permit arbitration to begin. By this technique a standard microprocessor such as an Intel 80386 can operate in such an architecture without being preempted from the bus (115) by the higher priority devices (140) to an extent that system operation deteriorates.
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公开(公告)号：DE3778010D1
公开(公告)日：1992-05-07
申请号：DE3778010
申请日：1987-12-15
Applicant: IBM
Inventor： HEATH CHESTER ASBURY , JACKSON KEVIN MICHAEL , JUDICE DARRYL EDMOND , PESTONJI HOSHANG RATAN
Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.
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