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    IMPROVED TLB MANAGEMENT FOR REAL-TIME APPLICATIONS
    2.
    发明申请
    IMPROVED TLB MANAGEMENT FOR REAL-TIME APPLICATIONS 审中-公开
    改进TLB管理实时应用程序

    公开(公告)号：WO2004053698A3

    公开(公告)日：2006-01-12

    申请号：PCT/GB0305108

    申请日：2003-11-21

    Applicant: IBM ,  IBM UK

    Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

    IPC: G06F12/10 ,  G06F12/12

    CPC classification number: G06F12/1027 ,  G06F12/126

    Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

    Abstract translation: 计算机系统中的存储器管理通过防止地址转换信息的一部分被替换为高速缓冲存储器中的其他类型的地址转换信息而被改进，该高速缓冲存储器被保留用于存储用于CPU更快速访问的这种地址转换信息。 这样，CPU可以识别存储在高速缓存中的地址转换信息的子集。

    Method and device for designing module
    3.
    发明专利
    Method and device for designing module 审中-公开
    用于设计模块的方法和设备

    公开(公告)号：JP2010272876A

    公开(公告)日：2010-12-02

    申请号：JP2010152027

    申请日：2010-07-02

    Applicant: Internatl Business Mach Corp ,  Sony Computer Entertainment Inc ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社ソニー・コンピュータエンタテインメント

    Inventor： KAHLE JAMES ALLAN ,  HARM PETER HOFSTEE ,  YAMAZAKI TAKESHI

    IPC: H01L21/82 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04

    CPC classification number: G06F17/5045

    Abstract: PROBLEM TO BE SOLVED: To minimize redesign time for a chip in chip design. SOLUTION: A modular design method provides a custom-designed chip by using variable and scalable module multiprocessor design, and without redesigning a module including design. The design includes a PU module, a plurality of first assist processing modules, and a plurality of first DMA control modules, with each being associated with different one of the plurality of assist processing modules. First multiprocessor design including one or more of the plurality of modules is generated, and the number of the modules to be reduced and/or added is selected, beforehand, from the first design. Furthermore, second multiprocessor design in which the selected number of the modules selected beforehand is reduced, and/or added is performed. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：为了最小化芯片设计芯片的重新设计时间。 解决方案：模块化设计方法通过使用可变和可扩展的模块多处理器设计提供定制设计的芯片，而无需重新设计包含设计的模块。 该设计包括PU模块，多个第一辅助处理模块和多个第一DMA控制模块，每个第一DMA控制模块与多个辅助处理模块中的不同的一个相关联。 产生包括多个模块中的一个或多个的第一多处理器设计，并且预先从第一设计中选择要减少和/或添加的模块的数量。 此外，其中预先选择的所选择的模块数量被减少和/或添加的第二多处理器设计。 版权所有（C）2011，JPO＆INPIT

    Method and device for designing module
    4.
    发明专利
    Method and device for designing module 审中-公开
    用于设计模块的方法和设备

    公开(公告)号：JP2007036223A

    公开(公告)日：2007-02-08

    申请号：JP2006191471

    申请日：2006-07-12

    Applicant: Internatl Business Mach Corp ,  Sony Computer Entertainment Inc ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社ソニー・コンピュータエンタテインメント

    Inventor： KAHLE JAMES ALLAN ,  HARM PETER HOFSTEE ,  YAMAZAKI TAKESHI

    IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04

    CPC classification number: G06F17/5045

    Abstract: PROBLEM TO BE SOLVED: To suppress the redesign time of a chip in chip designing to a minimum. SOLUTION: Disclose is a method of providing a custom design chip, without redesigning a module that includes design, in variable and scalable designing of a modular multiprocessor. A PU module, a first plurality of assist processing modules and a first plurality of DMA control modules, each being associated with different one of the plurality of assist processing modules are involved in this designing. A first multiprocessor design is created, including at least one module from among the plurality of modules, and the number of modules to be deleted and/or added is preliminarily selected from the first design. Furthermore, a second multiprocessor design is performed with preliminarily selected modules of the selected number deleted therefrom and/or are added thereto. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：将芯片设计中的芯片的重新设计时间抑制到最小。 解决方案：Disclose是一种在模块化多处理器的可变和可扩展设计中提供定制设计芯片的方法，而无需重新设计包含设计的模块。 在该设计中涉及PU模块，第一多个辅助处理模块和第一多个DMA控制模块，每个都与多个辅助处理模块中的不同的一个相关联。 创建第一多处理器设计，包括来自多个模块中的至少一个模块，并且从第一设计中预先选择要删除和/或添加的模块的数量。 此外，使用从其中删除的选定号码的预先选择的模块和/或添加到第二多处理器设计来执行第二多处理器设计。 版权所有（C）2007，JPO＆INPIT

    Cacheable dma
    5.
    发明专利
    Cacheable dma 有权
    可追加DMA

    公开(公告)号：JP2005056401A

    公开(公告)日：2005-03-03

    申请号：JP2004207889

    申请日：2004-07-14

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： KAHLE JAMES ALLAN

    IPC: G06F12/08 ,  G06F13/28

    CPC classification number: G06F13/28 ,  G06F12/0802 ,  G06F2212/251 ,  G06F2212/253

    Abstract: PROBLEM TO BE SOLVED: To provide a method and apparatus for loading data to a local store of a processor in a computer system having a direct memory access (DMA) mechanism. SOLUTION: A transfer of data is performed from a system memory of the computer system to the local store. The data is fetched from the system memory to a cache of the processor. A DMA read request is issued to request data. It is decided whether the requested data is found in the cache. Upon a decision that the requested data is found in the cache, the requested data is loaded directly from the cache to the local store. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于在具有直接存储器访问（DMA）机制的计算机系统中将数据加载到处理器的本地存储器的方法和装置。 解决方案：从计算机系统的系统存储器到本地存储器执行数据传输。 将数据从系统内存中读取到处理器的缓存。 发出DMA读取请求以请求数据。 确定在缓存中是否找到所请求的数据。 在确定在高速缓存中找到所请求的数据之后，所请求的数据直接从高速缓存加载到本地存储。 版权所有（C）2005，JPO＆NCIPI

    INFORMATION PROCESS SYSTEM AND ITS OPERATING METHOD
    7.
    发明专利
    INFORMATION PROCESS SYSTEM AND ITS OPERATING METHOD 失效

    公开(公告)号：JPH07121443A

    公开(公告)日：1995-05-12

    申请号：JP20317294

    申请日：1994-08-29

    Applicant: IBM

    Inventor： KAHLE JAMES ALLAN

    IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08

    Abstract: PURPOSE: To make a prefetch instruction valid by inputting 2nd information from a prefetch memory to a cache memory when 1st information includes the 2nd information and inputting the 2nd information from a system memory in the other case. CONSTITUTION: When target data information is not stored in a cache memory 12, a processor 16 judges whether this information is stored in a prefetch memory 26 or not and when it is stored, the processor 16 stores this data information from the prefetch memory 26 into the cache memory 12. When the target data information is not stored in the prefetch memory 26, the processor 16 requests this data information from a system memory 30 through a system bus 28. Afterwards, when a BIU 18 inputs the received data information, the processor 16 stores the information from a read register 24 into the cache memory 12.

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