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    PROCESSOR AND METHOD FOR SPECULATIVELY EXECUTING CONDITION BRANCHING COMMAND BY USING SELECTED ONE OF PLURAL BRANCH PREDICTION SYSTEM
    2.
    发明专利
    PROCESSOR AND METHOD FOR SPECULATIVELY EXECUTING CONDITION BRANCHING COMMAND BY USING SELECTED ONE OF PLURAL BRANCH PREDICTION SYSTEM 失效

    公开(公告)号：JPH10133873A

    公开(公告)日：1998-05-22

    申请号：JP10612897

    申请日：1997-04-23

    Applicant: IBM

    Inventor： MALLICK SOUMMYA ,  LOPER ALBERT JOHN

    IPC: G06F9/32 ,  G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To provide an improved processor and method for speculatively executing a condition branching command by using selected one of plural branch prediction systems. SOLUTION: The processor and the method for speculatively executing a branch command using a selected branch prediction system is disclosed. The processor has one or plural executing units for executing a command which includes a branch processing unit 18 for executing a branch command. In the branch processing unit 18, a selective logic mechanism 66 for selecting one of plural branch prediction systems, and a branch predicting unit for predicting a solution of a conditional branch command using the selected branch prediction system are included. In the branch processing unit 18, an executing function for speculatively executing the conditional branch command based on the prediction is further included. The selective logic mechanism 66 selects a branch prediction system for predicting the following conditional branch command based on the predicted result, and as a result, branch predictive accuracy is improved.

    Reducing power consumption in a processing device
    4.
    发明专利
    Reducing power consumption in a processing device 未知

    公开(公告)号：GB2317975A

    公开(公告)日：1998-04-08

    申请号：GB9716260

    申请日：1997-07-31

    Applicant: IBM

    Inventor： LOPER ALBERT J ,  MALLICK SOUMMYA

    IPC: G06F1/26 ,  G06F1/32 ,  G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0864

    Abstract: If a processor 10 is operating in a 'full-power' mode, a load/store unit 28, executing a load instruction directed to floating-point registers 36, loads 64 bits of data from a data cache 16 into a rename buffer 38 during a single processor cycle. If, however, the processor is operating in a 'special' power mode, then the 64 bits are loaded over two cycles instead (i.e. 32 bits per cycle), halving the number of sense amplifiers active at a time in the cache and so saving power. The maximum number of instructions fetched per cycle from an instruction cache 14, decoded and dispatched to execution units 20, 22, 26, 28, and the number of cache ways active at a time, may also be halved in the 'special' power-saving mode.

    5.
    发明专利
    未知

    公开(公告)号：DE69636861T2

    公开(公告)日：2007-07-05

    申请号：DE69636861

    申请日：1996-08-29

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  LOPER ALBERT J ,  MALLICK SOUMMYA ,  OGDEN AUBREY D

    IPC: G06F9/312 ,  G06F9/38 ,  G06F12/00

    Abstract: A load multiple instruction may be executed in a superscaler microprocessor by dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. A table is maintained that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. An instruction is executed that is dependent upon source operand data loaded by the load multiple instruction, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, a store multiple instruction may be executed by dispatching a store multiple instruction to the load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load/store instruction stores data from a plurality of registers to memory. A fixed point instruction is executed that is dependent upon data being stored by the store multiple instruction prior to the store multiple instruction completing its execution, but the executing fixed point instruction is prohibited from writing to a register of the plurality of registers prior to the store multiple instruction completing.

    6.
    发明专利
    未知

    公开(公告)号：DE69636861D1

    公开(公告)日：2007-03-15

    申请号：DE69636861

    申请日：1996-08-29

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  LOPER ALBERT J ,  MALLICK SOUMMYA ,  OGDEN AUBREY D

    IPC: G06F9/312 ,  G06F9/38 ,  G06F12/00

    Abstract: A load multiple instruction may be executed in a superscaler microprocessor by dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. A table is maintained that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. An instruction is executed that is dependent upon source operand data loaded by the load multiple instruction, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, a store multiple instruction may be executed by dispatching a store multiple instruction to the load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load/store instruction stores data from a plurality of registers to memory. A fixed point instruction is executed that is dependent upon data being stored by the store multiple instruction prior to the store multiple instruction completing its execution, but the executing fixed point instruction is prohibited from writing to a register of the plurality of registers prior to the store multiple instruction completing.

    Constructing and executing a program including out-of-order threads
    8.
    发明专利
    Constructing and executing a program including out-of-order threads 未知

    公开(公告)号：GB2321545A

    公开(公告)日：1998-07-29

    申请号：GB9724389

    申请日：1997-11-19

    Applicant: IBM

    Inventor： KAHLE JAMES ALLAN ,  MALLICK SOUMMYA ,  MCDONALD ROBERT G

    IPC: G06F9/44 ,  G06F9/48 ,  G06F9/38 ,  G06F9/45

    Abstract: In constructing a program, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread, i.e. the logical program order is to be reversed. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.

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