公开(公告)号：JP2001297000A

公开(公告)日：2001-10-26

申请号：JP2000391228

申请日：2000-12-22

Applicant: IBM

Inventor： KARL JAMES A ,  MORREY CHARLES R

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a processor, a data processing system and a processor instruction processing method related with this. SOLUTION: The processor is suited for dispatching an instruction to an issuing unit which includes the first-order issuing queue and the second-order issuing queue. The instruction is stored in the first-order issuing queue when it can be issued presently for execution and is stored in the second-order issuing queue when it cannot be issued presently. The processor decides an instruction to be issued next from the instruction of the first-order issuing queue. The instruction can be moved from the first-order issuing queue to the second-order issuing queue in the case of depending on the result of another instruction.

公开(公告)号：JP2001297001A

公开(公告)日：2001-10-26

申请号：JP2000391350

申请日：2000-12-22

Applicant: IBM

Inventor： KARL JAMES A

IPC: G06F9/38 ,  G06F20060101 ,  G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide a processor, a data processing system, and an executing method relating thereto. SOLUTION: The processor suitably receives a set of instructions and compiles the instruction set into an instruction group. The instruction group is dispatched for execution. After the instruction group is executed, instruction history information showing an exception event relating to the instruction group is recorded. Then the execution of instructions is changed in response to the instruction history information and an exception event is prevented from being generated at the time of execution after the instruction group. The processor includes a storage mechanism, such as an instruction cache, an L2 cache, and a system memory, a cracking unit, and a basic cache block.

公开(公告)号：JP2002149401A

公开(公告)日：2002-05-24

申请号：JP2001298397

申请日：2001-09-27

Applicant: IBM

Inventor： KARL JAMES A ,  MOORE CHARLES ROBERTS

IPC: G06F9/38 ,  G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/32

Abstract: PROBLEM TO BE SOLVED: To select a microprocessor for converting an instruction set in an existing format into an inside instruction set suitable for a high speed operation. SOLUTION: At first, the sequence of instructions is inputted to a cracking unit 212 of a microprocessor. A code sequence recognizing unit(CSR) 402 is constituted so that a short branch sequence in the instruction sequence can be detected. The short branch sequence includes a condition setting instruction, condition branch, and at least one additional instruction to be executed when the condition branch is not performed. The short branch sequence is converted into a predictive part instruction sequence inside. The predictive part instruction sequence includes the condition setting instruction and a predictive part instruction corresponding to the respective additional instructions of the short branch sequence. The predictive part instruction sequence is executed by at least one functioning unit of the processor.

公开(公告)号：JP2001229024A

公开(公告)日：2001-08-24

申请号：JP2000391300

申请日：2000-12-22

Applicant: IBM

Inventor： KARL JAMES A

IPC: G06F9/38 ,  G06F20060101 ,  G06F9/30 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide a microprocessor using an instruction group and a cache mechanism matched with an instruction group format. SOLUTION: This microprocessor is provided with an instruction cracking unit constituted so that the first set of microprocessor instructions can be received, and the cracking unit compiles the set of the instructions as an instruction group. The instructions of the group are respectively provided with an instruction group tag. The processor is constituted of a basic cache block mechanism compiled with an instruction group format for caching the instruction group generated by the cracking unit.