公开(公告)号：JP2002149401A

公开(公告)日：2002-05-24

申请号：JP2001298397

申请日：2001-09-27

Applicant: IBM

Inventor： KARL JAMES A ,  MOORE CHARLES ROBERTS

IPC: G06F9/38 ,  G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/32

Abstract: PROBLEM TO BE SOLVED: To select a microprocessor for converting an instruction set in an existing format into an inside instruction set suitable for a high speed operation. SOLUTION: At first, the sequence of instructions is inputted to a cracking unit 212 of a microprocessor. A code sequence recognizing unit(CSR) 402 is constituted so that a short branch sequence in the instruction sequence can be detected. The short branch sequence includes a condition setting instruction, condition branch, and at least one additional instruction to be executed when the condition branch is not performed. The short branch sequence is converted into a predictive part instruction sequence inside. The predictive part instruction sequence includes the condition setting instruction and a predictive part instruction corresponding to the respective additional instructions of the short branch sequence. The predictive part instruction sequence is executed by at least one functioning unit of the processor.

公开(公告)号：DE69327288T2

公开(公告)日：2000-06-08

申请号：DE69327288

申请日：1993-09-20

Applicant: IBM

Inventor： MOORE CHARLES ROBERTS ,  MUHICH JOHN STEPHEN

IPC: G06F12/08 ,  G06F12/10 ,  G06F15/16 ,  G06F15/177

Abstract: Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translation lookaside buffer (TLB) for translating effective addresses to real addresses and coherency between all translation lookaside buffers (TLB) must therefore be maintained. The method and system disclosed herein may be utilized to broadcast a unique bus structure in response to an execution of a translation lookaside buffer invalidate (TLBI) instruction by any processor within a multiprocessor system. The bus structure is accepted by other processors along the bus only in response to an absence of a pending translation lookaside buffer invalidate (TLBI) instruction within each processor. Thus, a broadcast translation lookaside buffer invalidate (TLBI) instruction may only be executed by the other processors within a multiprocessor system if it has been accepted by all processors within the system. After initiating execution of a translation lookaside buffer invalidate (TLBI) instruction at all processors within the system, the execution of pending instructions is temporarily terminated until after the translation lookaside buffer invalidate (TLBI) instruction has been executed. Thereafter, the execution of instructions is suspended until all read and write operations within the memory queue have achieved coherency. Next, all suspended and/or prefetched instructions are refetched utilizing the modified translation lookaside buffer (TLB) to ensure that the address utilized is still valid.

公开(公告)号：HK1037248A1

公开(公告)日：2002-02-01

申请号：HK01106811

申请日：2001-09-27

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  MOORE CHARLES ROBERTS

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F

Abstract: A processor and data processing system suitable for dispatching an instruction to an issue unit. The issue unit includes a primary issue queue and a secondary issue queue. The instruction is stored in the primary issue queue if the instruction is currently eligible to issue for execution. The instruction is stored in the secondary issue queue if the instruction is currently ineligible to issue for execution. An instruction may be moved from the primary issue queue to the secondary issue queue if instruction is dependent upon results from another instruction. In one embodiment, the instruction may be moved from the primary issue queue to the secondary issue queue after issuing the instruction for execution. In this embodiment, the instruction may be maintained in the secondary issue queue for a specified duration. Thereafter, the secondary issue queue entry containing the instruction is deallocated if the instruction has not been rejected.

公开(公告)号：FR2800482B1

公开(公告)日：2003-06-13

申请号：FR0011605

申请日：2000-09-12

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  LE HUNG QUI ,  MOORE CHARLES ROBERTS

IPC: G06F9/38 ,  G06F15/04

Abstract: A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.

公开(公告)号：FR2800482A1

公开(公告)日：2001-05-04

申请号：FR0011605

申请日：2000-09-12

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  LE HUNG QUI ,  MOORE CHARLES ROBERTS

IPC: G06F9/38 ,  G06F15/04

Abstract: The instruction handling reads a set of instructions and organizes them into a group of instructions in which each instruction shares a common group label, indicating its order in relation to other instruction groups. An entry in an execution table is attributed to the instruction group to track execution state, with the group label recorded in the instruction table as instructions are executed.

公开(公告)号：CA2356805A1

公开(公告)日：2003-03-07

申请号：CA2356805

申请日：2001-09-07

Applicant: IBM

Inventor： MOORE CHARLES ROBERTS ,  KAHLE JAMES ALLAN

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F15/76

Abstract: A microprocessor and method of processing instructions therein are disclosed . Initially, a sequence of instructions is dispatched by a dispatch unit of the microprocessor. A code sequence recognition unit (CSR) is configured to detect a short branch sequence withi n the sequence of instruction, where the short branch sequence includes a condition setting instruction, a conditional branch, and at least one additional instruction that is executed if the conditional branch is not taken. The short branch sequence is then internally converted to a predicated instruction sequence that includes the condition setting instruction and a predicated instruction corresponding to each additional instruction in the short branch sequence. The predicated instruction sequence is then executed in at least one functional unit of the processor. Detecting the sho rt branch sequence may include calculating the relative branch address associated with the conditional branch instruction and comparing the relative branch address to a specified maximum. In one embodiment, the received sequence of instructions may be converted into an instruction group by the processor. In this embodiment, the specified maximum number of instructions in a short branch sequence may be a function of the number of instructions in an instructiongroup. In an embodiment where the conditional branch statement is preferably allocated to the last slot of the instruction group, the additional instructions in the short branch sequence are located in the next subsequent instruction group. Converting the short branch sequence to the predicated instruction sequence may include converting each additional instruction in the short branch sequence to an analogous predicated instruction. In one embodiment, converting each additional instruction to it s analogous predicated instruction includes determining a predicated instruction opcode for each additional instruction in the short branch sequence by adjusting the opcode of each additional instruction by a predetermined offset. In another embodiment, the opcode conversion may be accomplished wit h an opcode lookup table.

公开(公告)号：DE69327288D1

公开(公告)日：2000-01-20

申请号：DE69327288

申请日：1993-09-20

Applicant: IBM

Inventor： MOORE CHARLES ROBERTS ,  MUHICH JOHN STEPHEN

IPC: G06F12/08 ,  G06F12/10 ,  G06F15/16 ,  G06F15/177

Abstract: Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translation lookaside buffer (TLB) for translating effective addresses to real addresses and coherency between all translation lookaside buffers (TLB) must therefore be maintained. The method and system disclosed herein may be utilized to broadcast a unique bus structure in response to an execution of a translation lookaside buffer invalidate (TLBI) instruction by any processor within a multiprocessor system. The bus structure is accepted by other processors along the bus only in response to an absence of a pending translation lookaside buffer invalidate (TLBI) instruction within each processor. Thus, a broadcast translation lookaside buffer invalidate (TLBI) instruction may only be executed by the other processors within a multiprocessor system if it has been accepted by all processors within the system. After initiating execution of a translation lookaside buffer invalidate (TLBI) instruction at all processors within the system, the execution of pending instructions is temporarily terminated until after the translation lookaside buffer invalidate (TLBI) instruction has been executed. Thereafter, the execution of instructions is suspended until all read and write operations within the memory queue have achieved coherency. Next, all suspended and/or prefetched instructions are refetched utilizing the modified translation lookaside buffer (TLB) to ensure that the address utilized is still valid.