公开(公告)号：DE3176585D1

公开(公告)日：1988-02-04

申请号：DE3176585

申请日：1981-10-09

Applicant: IBM

Inventor： DAVIDSON EVAN EZRA ,  KATOPIS GEORGE ALEXANDER ,  RUBIN BARRY JAY

IPC: H03K19/0175 ,  G05F1/46 ,  H01L27/00 ,  H01L27/01 ,  H04B15/00 ,  H04L25/08 ,  H01L23/56

Abstract: A clamping circuit to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips (Chip 1, Chip 2) and the chips have a power supply (V cc ) and power leads respectively. An impedance path is defined between each of the chips (Chip 1, Chip 2) and the power supply (V cc ) to define a current path for switching noise through the top of the module. A high impedance path is defined for voltages below a predetermined upper limit (V1) of the chip supply voltage and a low impedance path is defined by the clamping circuit for the voltage range where noise superimposed on the chip supply voltage occurs.