公开(公告)号：DE2753570A1

公开(公告)日：1978-06-08

申请号：DE2753570

申请日：1977-12-01

Applicant: IBM

Inventor： ANANTHA NARASIPUR ,  CHANG FUNG YUEL ,  RUBIN BARRY JAY

IPC: G11C27/04 ,  G11C11/56 ,  G11C19/28 ,  G11C19/36 ,  H03H11/26 ,  G11C19/18

公开(公告)号：DE2835497A1

公开(公告)日：1979-03-01

申请号：DE2835497

申请日：1978-08-12

Applicant: IBM

Inventor： CASES MOISES ,  CHANG FUNG YUEL ,  RUBIN BARRY JAY

IPC: G06G7/16 ,  G11C27/04 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H03H15/02 ,  H03H11/00

Abstract: A charge coupled device analog multiplier is used to weigh the sampled and delayed signals for a transversal filter. The digital filter coefficients for the analog multiplier can be electrically programmed and therefore dynamic time-varying systems, such as matched filters, can be designed with reduced circuit complexity. The digital filter includes means for sampling without destroying an analog signal at various points and providing voltages proportional to each sampled signal. The voltages are separately applied to a charge coupled device analog multiplier which accepts the voltages and provides means for multiplying the digital filter coefficient by the analog voltage. The multiplied sample signal is then dumped into a means for summing all of the weighted sample signals to produce an analog signal modified by the digital filter coefficients.

公开(公告)号：DE3176585D1

公开(公告)日：1988-02-04

申请号：DE3176585

申请日：1981-10-09

Applicant: IBM

Inventor： DAVIDSON EVAN EZRA ,  KATOPIS GEORGE ALEXANDER ,  RUBIN BARRY JAY

IPC: H03K19/0175 ,  G05F1/46 ,  H01L27/00 ,  H01L27/01 ,  H04B15/00 ,  H04L25/08 ,  H01L23/56

Abstract: A clamping circuit to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips (Chip 1, Chip 2) and the chips have a power supply (V cc ) and power leads respectively. An impedance path is defined between each of the chips (Chip 1, Chip 2) and the power supply (V cc ) to define a current path for switching noise through the top of the module. A high impedance path is defined for voltages below a predetermined upper limit (V1) of the chip supply voltage and a low impedance path is defined by the clamping circuit for the voltage range where noise superimposed on the chip supply voltage occurs.

公开(公告)号：DE2734942A1

公开(公告)日：1978-05-03

申请号：DE2734942

申请日：1977-08-03

Applicant: IBM

Inventor： RUBIN BARRY JAY

IPC: H03M1/66 ,  H01L21/339 ,  H01L29/762 ,  H01L29/768 ,  H03M1/00 ,  H03K13/02