公开(公告)号：BR8502592A

公开(公告)日：1986-02-04

申请号：BR8502592

申请日：1985-05-30

Applicant: IBM

Inventor： OVIES HERNANDO ,  KATZ NEIL IAN ,  FARRELL ROBERT HENRY ,  BAKER ERNEST D

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/08 ,  G06F13/14

Abstract: An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a buffer RAM through registers to the respective memories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.