公开(公告)号：JPS617967A

公开(公告)日：1986-01-14

申请号：JP1565085

申请日：1985-01-31

Applicant: Ibm

Inventor： BAKER ERNEST D ,  FARRELL ROBERT HENRY ,  KATZ NEIL ALAN ,  OVIES HERNANDO

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0866

公开(公告)号：AU4193585A

公开(公告)日：1985-12-19

申请号：AU4193585

申请日：1985-05-03

Applicant: IBM

Inventor： BAKER ERNEST D ,  FARRELL ROBERT H ,  KATZ NEIL A ,  OVIES HERNANDO

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/08 ,  G06F13/38

Abstract: An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a buffer RAM through registers to the respective memories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.

公开(公告)号：DE3586299T2

公开(公告)日：1993-04-15

申请号：DE3586299

申请日：1985-04-30

Applicant: IBM

Inventor： BAKER ERNEST D ,  FARRELL ROBERT HENRY ,  KATZ NEIL ALAN ,  OVIES HERNANDO

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/08

Abstract: An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a buffer RAM through registers to the respective memories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.

公开(公告)号：CA1235231A

公开(公告)日：1988-04-12

申请号：CA478633

申请日：1985-04-09

Applicant: IBM

Inventor： BAKER ERNEST D ,  FARRELL ROBERT H ,  KATZ NEIL A ,  OVIES HERNANDO

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/08 ,  G06F13/20

Abstract: I/O CONTROLLER FOR MULTIPLE DISPARATE SERIAL MEMORIES WITH A CACHE An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a A buffer RAM through registers to the respective memories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.

公开(公告)号：DE3586299D1

公开(公告)日：1992-08-13

申请号：DE3586299

申请日：1985-04-30

Applicant: IBM

Inventor： BAKER ERNEST D ,  FARRELL ROBERT HENRY ,  KATZ NEIL ALAN ,  OVIES HERNANDO

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/08

Abstract: An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a buffer RAM through registers to the respective memories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.

公开(公告)号：BR8502592A

公开(公告)日：1986-02-04

申请号：BR8502592

申请日：1985-05-30

Applicant: IBM

Inventor： OVIES HERNANDO ,  KATZ NEIL IAN ,  FARRELL ROBERT HENRY ,  BAKER ERNEST D

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/08 ,  G06F13/14

Abstract: An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a buffer RAM through registers to the respective memories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.