公开(公告)号：US3649817A

公开(公告)日：1972-03-14

申请号：US3649817D

申请日：1970-07-29

Applicant: IBM

Inventor： KELLER GUNTER ,  KNAUFT GUENTER ,  SKUIN PETAR ,  VOGT EDWIN

IPC: G06F7/38 ,  G06F7/00 ,  G06F7/499 ,  G06F7/508 ,  G06F11/10 ,  H03K19/00

CPC classification number: G06F11/10

Abstract: In an arithmetic and logical unit suitable for ''''Adding,'''' ''''AND,'''' ''''OR'''' and ''''Exclusive OR'''' operations, additions are performed to the carry-dependent sum formation principle, while during the execution of logical operations, operand bit parity functions related to the respective operation are generated by means of a function generator. In an operation-dependent checking circuit the carries of additions or the parity functions of logical operations are combined for result parity prediction independently of the sum formed. For error-checking the result, the parity of the result bits is compared for compliance with the predicted parity.

Abstract translation: 在适用于“添加”，“与”，“或”和“异或”运算的算术和逻辑单元中，对进位依赖和形成原理进行加法，而在执行逻辑运算期间，操作数位奇偶校验函数 通过函数发生器产生与相应操作有关的信息。 在与操作相关的检查电路中，独立于形成的和，将逻辑运算的加法或奇偶校验功能的组合用于结果奇偶校验。 为了错误检查结果，比较结果位的奇偶校验符合预测的奇偶校验。