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    Arithmetic and logical unit with error checking
    1.
    发明授权
    Arithmetic and logical unit with error checking 失效
    具有错误检查的算术和逻辑单元

    公开(公告)号：US3649817A

    公开(公告)日：1972-03-14

    申请号：US3649817D

    申请日：1970-07-29

    Applicant: IBM

    Inventor： KELLER GUNTER ,  KNAUFT GUENTER ,  SKUIN PETAR ,  VOGT EDWIN

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/499 ,  G06F7/508 ,  G06F11/10 ,  H03K19/00

    CPC classification number: G06F11/10

    Abstract: In an arithmetic and logical unit suitable for ''''Adding,'''' ''''AND,'''' ''''OR'''' and ''''Exclusive OR'''' operations, additions are performed to the carry-dependent sum formation principle, while during the execution of logical operations, operand bit parity functions related to the respective operation are generated by means of a function generator. In an operation-dependent checking circuit the carries of additions or the parity functions of logical operations are combined for result parity prediction independently of the sum formed. For error-checking the result, the parity of the result bits is compared for compliance with the predicted parity.

    Abstract translation: 在适用于“添加”，“与”，“或”和“异或”运算的算术和逻辑单元中，对进位依赖和形成原理进行加法，而在执行逻辑运算期间，操作数位奇偶校验函数 通过函数发生器产生与相应操作有关的信息。 在与操作相关的检查电路中，独立于形成的和，将逻辑运算的加法或奇偶校验功能的组合用于结果奇偶校验。 为了错误检查结果，比较结果位的奇偶校验符合预测的奇偶校验。

    2.
    发明专利
    未知

    公开(公告)号：DE2131787A1

    公开(公告)日：1973-01-11

    申请号：DE2131787

    申请日：1971-06-26

    Applicant: IBM DEUTSCHLAND

    Inventor： HAJDU JOHANN ,  SKUIN PETAR ,  VOGT EDWIN DR ,  ROLAND GENG HELLMUTH

    IPC: G06F11/08 ,  G06F11/10 ,  H04L1/00 ,  H03K13/32

    Abstract: In a data processing system, a first processing unit is connected to several other processing units by one transfer bus each for the two directions of transmission, a circuit arrangement for error detection being associated with the transfer lines. The first unit comprises a check character generator generating a parity check character both for the information to be transferred from the first processing unit to the further processing units and from the further processing units to the first processing unit. The transfer lines of both directions are provided with a common transfer path, by means of which the parity check characters generated by the check character generator are transferred from the first unit to the further units. Each of the further units comprises a check circuit connected to the two transfer buses and the check character transfer path and checking the correctness of the transferred information for both directions of transmission.

    CIRCUIT ARRANGEMENT FOR ERROR DETECTION IN DATA PROCESSING SYSTEMS
    3.
    发明专利
    CIRCUIT ARRANGEMENT FOR ERROR DETECTION IN DATA PROCESSING SYSTEMS 未知

    公开(公告)号：CA955686A

    公开(公告)日：1974-10-01

    申请号：CA145363

    申请日：1972-06-22

    Applicant: IBM

    Inventor： GENG HELLMUTH R ,  HAJDU JOHANN ,  SKUIN PETAR ,  VOGT EDWIN

    IPC: G06F11/08 ,  G06F11/10 ,  H04L1/00

    Abstract: In a data processing system, a first processing unit is connected to several other processing units by one transfer bus each for the two directions of transmission, a circuit arrangement for error detection being associated with the transfer lines. The first unit comprises a check character generator generating a parity check character both for the information to be transferred from the first processing unit to the further processing units and from the further processing units to the first processing unit. The transfer lines of both directions are provided with a common transfer path, by means of which the parity check characters generated by the check character generator are transferred from the first unit to the further units. Each of the further units comprises a check circuit connected to the two transfer buses and the check character transfer path and checking the correctness of the transferred information for both directions of transmission.

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