POST CMP POROGEN BURN OUT PROCESS

    公开(公告)号:AU2003282483A1

    公开(公告)日:2004-08-10

    申请号:AU2003282483

    申请日:2003-10-09

    Applicant: IBM

    Abstract: A method and structure for forming an integrated circuit structure is disclosed that forms at least one first layer comprising logical and functional devices and forms at least one interconnection layer above the first layer. The interconnection layer is adapted to form electrical connections between the logical and functional devices. The interconnection layer is made by first forming a dielectric layer. The dielectric layer includes a first material and a second material, wherein the second material is less stable at manufacturing environmental conditions (e.g., the processing conditions discussed below) than the first material. The "second material" comprises a porogen and the "first material" comprises a matrix polymer. The invention then forms conductive features in the dielectric layer and removes (e.g., by heating) the second material from the dielectric layer to create air pockets in the interconnection layer where the second material was positioned.

Patent Agency Ranking