公开(公告)号：JP2000190300A

公开(公告)日：2000-07-11

申请号：JP21079199

申请日：1999-07-26

Applicant: IBM

Inventor： BLACK CHARLES T ,  STEPHEN M GATES ,  MURRAY CHRISTOPHER B ,  SUN SHOUHEN

IPC: B82B1/00 ,  C01G49/00 ,  C07B61/00 ,  C12N15/10 ,  G11B5/62 ,  G11B5/84 ,  H01F1/00 ,  H01F1/047

Abstract: PROBLEM TO BE SOLVED: To form a stratification structure of nano-meter(nm) scale particles by placing a lattice-shaped lattice layer containing deoxyribo nucleic acid(DNA) so as to form a cell of the lattice layer on the surface of a substrate, and arranging a single particle in each cell. SOLUTION: A lattice constant of a stratification structure (a second lattice) of nano-meter scale particles is controlled by a lattice layer coincident in DNA. A DNA lattice (a first lattice) is manufactured using an automatic synthesizing method, this arrangement causes DNA to form a regular arrangement in an opening or a lattice site by self organization so as to include a specific nucleotide base arrangement. Then (a) a substrate 1 having a surface, (b) the lattice- shaped lattice layer containing a DNA segment arranged so as to form a cell of the lattice layer are arranged on the surface of the substrate 1, and (c) at least one particle 3 is placed in each cell. Thus, a stratification structure of nano-meter scale particles can be easily formed.

公开(公告)号：AU2003282483A1

公开(公告)日：2004-08-10

申请号：AU2003282483

申请日：2003-10-09

Applicant: IBM

Inventor： SATYANARAYANA NITTA ,  CHRISTY S TYBERG ,  SHYNG-TSONG CHEN ,  STEPHEN M GATES ,  JEFFREY C HEDRICK ,  KELLY MALONE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/302 ,  H01L21/31 ,  H01L23/48 ,  H01L23/52 ,  H01L21/00

Abstract: A method and structure for forming an integrated circuit structure is disclosed that forms at least one first layer comprising logical and functional devices and forms at least one interconnection layer above the first layer. The interconnection layer is adapted to form electrical connections between the logical and functional devices. The interconnection layer is made by first forming a dielectric layer. The dielectric layer includes a first material and a second material, wherein the second material is less stable at manufacturing environmental conditions (e.g., the processing conditions discussed below) than the first material. The "second material" comprises a porogen and the "first material" comprises a matrix polymer. The invention then forms conductive features in the dielectric layer and removes (e.g., by heating) the second material from the dielectric layer to create air pockets in the interconnection layer where the second material was positioned.