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    Method of fabricating solid-state devices
    1.
    发明授权
    Method of fabricating solid-state devices 失效
    制造固态装置的方法

    公开(公告)号：US3642544A

    公开(公告)日：1972-02-15

    申请号：US3642544D

    申请日：1968-10-07

    Applicant: IBM

    Inventor： KEYES ROBERT W ,  WEISER KURT

    IPC: H01L21/00 ,  H01L33/00 ,  H01L7/36 ,  H01L7/44

    CPC classification number: H01L33/0029 ,  H01L21/00 ,  H01L33/00 ,  Y10S148/056 ,  Y10S148/065 ,  Y10S438/917

    Abstract: An electroluminescent diode with a negative resistance characteristic at room temperature is obtained by establishing a host semiconductor substrate of gallium arsenide crystal with a deep level acceptor impurity such as manganese as the dominant dopant thereby obtaining a P-type semiconductor. On a surface of the gallium arsenide there is epitaxially grown, e.g., by vapor epitaxy, a region of gallium arsenide doped with an N-type dopant, e.g., tellurium. The latter region provides injection of electrons, the minority carriers, into the high-resistivity region when suitable voltage is applied across the diode. On another surface of the host gallium arsenide substrate removed from the tellurium doped region, a shallow level impurity such as zinc is diffused therein to obtain a region dominated thereby. The diffusion produces a high-resistivity zone bounded by the zinc and manganese dominant regions. At room temperature, e.g., 20* C., and below, the diode shows a high-series resistance at voltages beyond approximately 1 volt. When a critical breakdown voltage is reached, a negative resistance is obtained in which the current goes up with decreasing voltage. The switching speed of the diode from low- to high-current operations is less than 10 nanoseconds for an overvoltage of the order of 1 volt.

    Abstract translation: 通过以诸如锰作为主要掺杂剂的深层受主杂质建立砷化镓晶体的主体半导体衬底，获得室温下具有负电阻特性的电致发光二极管，从而获得P型半导体。 在砷化镓的表面上，例如通过蒸气外延外延生长掺杂有N型掺杂剂例如碲的砷化镓的区域。 当在二极管上施加合适的电压时，后一区域提供电子（少数载流子）注入高电阻率区域。 在从碲掺杂区域去除的主体砷化镓衬底的另一个表面上，诸如锌的浅层杂质扩散到其中，从而获得由此控制的区域。 扩散产生由锌和锰主导区域界定的高电阻率区域。

    METHOD FOR FABRICATING ULTRA-NARROW METALLIC LINES
    9.
    发明专利
    METHOD FOR FABRICATING ULTRA-NARROW METALLIC LINES 未知

    公开(公告)号：CA1092727A

    公开(公告)日：1980-12-30

    申请号：CA292938

    申请日：1977-12-13

    Applicant: IBM

    Inventor： HARRIS ERIK P ,  KEYES ROBERT W

    IPC: B21C37/04 ,  C23C14/48 ,  C23F1/02 ,  C23F4/00 ,  H01L21/306 ,  H01L21/768 ,  H01L39/24

    Abstract: METHOD FOR FABRICATING ULTRA-NARROW METALLIC LINES A method for fabricating very narrow superconducting metallic lines on a substrate using ion-implantation and etching techniques. The method permits lines to be produced which are much smaller than those fabricated by conventional masking and etching techniques. It makes the fabrication of very small Josephson and other superconducting devices possible. Also since lines are formed in metals, they have high conductivity, so are useful as ordinary conductors at high temperature or when the technique is utilized with non-superconducting materials. The method includes the steps of depositing a selected metal film on a substrate, applying a photoresist or other masking pattern and exposing, etching away the exposed region, ion-implanting the edge of the resulting pattern, removing the photoresist and etching away the unimplanted portion of the metal leaving an ultra-narrow line pattern.

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