TRANSISTOR ARRAY ARRANGEMENT
    1.
    发明专利

    公开(公告)号:DE3377557D1

    公开(公告)日:1988-09-01

    申请号:DE3377557

    申请日:1983-12-21

    Applicant: IBM

    Abstract: A transistor array arrangement for providing high-density semiconductor logic circuits in double polysilicon technology is described. Semiconductor, for example, FET, logic circuits have four independent but simultaneously accessible FET devices which are formed by intersecting sets of polysilicon gate lines. The four FET devices share a common first diffusion, for example a source, surrounded by four logically independent second diffusions, for example drains. A three-bit decode device is made which includes this array design.

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