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公开(公告)号：DE69218076D1
公开(公告)日：1997-04-17
申请号：DE69218076
申请日：1992-08-10
Applicant: IBM
Inventor： BERTIN CLAUDE LOUIS , FARRAR PAUL ALDEN , KALTER HOWARD LEO , KELLEY GORDON ARTHUR , VAN DER HOEVEN WILLEM BERNARD , WHITE FRANCIS ROGER
IPC: H01L27/00 , H01L25/065 , H01L25/07 , H01L25/18
Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip (50) having high aspect ratio metallized trenches (62) therein extending from a first surface to a second surface (58) thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate (52). Next the integrated circuit device is affixed to a carrier (70) such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches (66). Specific details of the fabrication method and the resultant multichip package are set forth.
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公开(公告)号：NZ232458A
公开(公告)日：1992-03-26
申请号：NZ23245890
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU615373B2
公开(公告)日：1991-09-26
申请号：AU4939990
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE3170944D1
公开(公告)日：1985-07-18
申请号：DE3170944
申请日：1981-10-09
Applicant: IBM
Inventor： KALTER HOWARD LEO , KOTECHA HARISH NARANDAS , PATEL PARSOTAM TRIKAM
IPC: H01L27/112 , G11C14/00 , H01L21/8246 , H01L21/8247 , H01L29/788 , H01L29/792 , G11C11/00
Abstract: The non-volatile semiconductor memory includes a one device dynamic volatile memory cell having a storage capacitor (C5) with a plate (12) and a storage node (10) coupled to a non-volatile device having a floating gate (FG), a control gate (24) and a voltage divider (16) having first and second serially-connected capacitors (C1, C2), with the floating gate (FG) being disposed at the common point between the first and second capacitors. The plate (12) of the storage capacitor is connected to a reference voltage source. The control gate (24) is preferably capacitively coupled to the floating gate (FG) through the first (C1) capacitor which includes a dual charge or electron injector structure (26). The capacitance of the first capacitor (C1) has a value substantially less than that of the second capacitor (C2).
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公开(公告)号：CH607231A5
公开(公告)日：1978-11-30
申请号：CH611276
申请日：1976-05-17
Applicant: IBM
Inventor： KALTER HOWARD LEO
IPC: G11C11/419 , G11C11/409 , G11C11/4091 , H03K3/353 , G11C7/06 , H03K6/02
Abstract: A high speed ratioless FET sense amplifier for sensing stored information in a semiconductor memory system. The amplifier is capable of sensing very small voltage signals provided by charges stored in a plurality of single FET/capacitor memory cells. The amplifier comprises a pair of cross-coupled FET devices coupled to a pair of bit/sense lines by clock signal responsive switching devices. The source electrodes of the cross-coupled FETs are each independently capacitively coupled to another clock signal and also to a source of low potential through a pair of clock driven source pull-down FETs. The amplifier uses minimal size devices and is process parameter independent.
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Patent Agency Ranking
公开(公告)号：DE2621137A1
公开(公告)日：1976-12-02
申请号：DE2621137
申请日：1976-05-13
Applicant: IBM
Inventor： KALTER HOWARD LEO
IPC: G11C11/419 , G11C11/409 , G11C11/4091 , H03K3/353 , G11C7/06
Abstract: A high speed ratioless FET sense amplifier for sensing stored information in a semiconductor memory system. The amplifier is capable of sensing very small voltage signals provided by charges stored in a plurality of single FET/capacitor memory cells. The amplifier comprises a pair of cross-coupled FET devices coupled to a pair of bit/sense lines by clock signal responsive switching devices. The source electrodes of the cross-coupled FETs are each independently capacitively coupled to another clock signal and also to a source of low potential through a pair of clock driven source pull-down FETs. The amplifier uses minimal size devices and is process parameter independent.
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公开(公告)号：DE69218076T2
公开(公告)日：1997-09-18
申请号：DE69218076
申请日：1992-08-10
Applicant: IBM
Inventor： BERTIN CLAUDE LOUIS , FARRAR PAUL ALDEN , KALTER HOWARD LEO , KELLEY GORDON ARTHUR , VAN DER HOEVEN WILLEM BERNARD , WHITE FRANCIS ROGER
IPC: H01L27/00 , H01L25/065 , H01L25/07 , H01L25/18
Abstract: A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip (50) having high aspect ratio metallized trenches (62) therein extending from a first surface to a second surface (58) thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate (52). Next the integrated circuit device is affixed to a carrier (70) such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches (66). Specific details of the fabrication method and the resultant multichip package are set forth.
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公开(公告)号：DE68923811T2
公开(公告)日：1996-04-18
申请号：DE68923811
申请日：1989-03-09
Applicant: IBM
Inventor： FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , MILLER CHRISTOPHER PAUL , TOMASHOT STEVEN WILLIAM
IPC: G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G06F11/20
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公开(公告)号：DE69021413T2
公开(公告)日：1996-03-21
申请号：DE69021413
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69021413D1
公开(公告)日：1995-09-14
申请号：DE69021413
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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