公开(公告)号：WO2008037634B1

公开(公告)日：2008-05-15

申请号：PCT/EP2007059858

申请日：2007-09-18

Applicant: IBM ,  IBM UK ,  CHO CHOONGYEUN ,  KIM DAEIK ,  KIM JONGHAE ,  KIM MOON JU ,  PLOUCHART JEAN-OLIVIER ,  TRZCINSKI ROBERT

Inventor： CHO CHOONGYEUN ,  KIM DAEIK ,  KIM JONGHAE ,  KIM MOON JU ,  PLOUCHART JEAN-OLIVIER ,  TRZCINSKI ROBERT

IPC: H01L21/02 ,  G06F17/50 ,  H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L23/64 ,  H01L27/02

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more of chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

Abstract translation: 提供用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化芯片产量，芯片性能，芯片制造性和电感器Q因子参数中的一个或多个。

公开(公告)号：AT532264T

公开(公告)日：2011-11-15

申请号：AT09782812

申请日：2009-09-09

Applicant: IBM

Inventor： KIM MOON ,  KIM DAEIK ,  CHO CHOONGYEUN ,  CORBIN ELMER

IPC: H03K19/00

Abstract: The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture.