公开(公告)号：US3493958A

公开(公告)日：1970-02-03

申请号：US49379865

申请日：1965-10-07

Applicant: IBM

Inventor： GORBATENKO GEORGE G ,  KIMMEL MILTON J

IPC: H03M1/14 ,  G06F7/02 ,  G06F7/50 ,  G06F7/505 ,  H01H33/30 ,  H03K20060101 ,  H03M1/00 ,  H04L3/00 ,  G06F5/02

CPC classification number: G06F7/505 ,  G06F7/026 ,  G06F2207/384 ,  H01H33/30 ,  H03M1/00 ,  H03M1/1066

公开(公告)号：US3460131A

公开(公告)日：1969-08-05

申请号：US47425565

申请日：1965-07-23

Applicant: IBM

Inventor： GORBATENKO GEORGE G ,  JURSIK JAMES ,  KIMMEL MILTON J ,  RAZI SYED ,  WILSON NORMAN D

IPC: H03M1/14 ,  G06F7/02 ,  G06F7/50 ,  G06F7/505 ,  H01H33/30 ,  H03K20060101 ,  H03M1/00 ,  H03K13/02

CPC classification number: G06F7/505 ,  G06F7/026 ,  G06F2207/384 ,  H01H33/30 ,  H03M1/00 ,  H03M1/1066

公开(公告)号：CA800170A

公开(公告)日：1968-11-26

申请号：CA800170D

Applicant: IBM

Inventor： GORBATENKO GEORGE G ,  KIMMEL MILTON J

公开(公告)号：CA1236229A

公开(公告)日：1988-05-03

申请号：CA477752

申请日：1985-03-28

Applicant: IBM

Inventor： BROWN MARK W ,  DUBKE ROBERT E ,  KIMMEL MILTON J

IPC: G06T11/20 ,  G09G5/20 ,  G09G1/00

Abstract: HARDWARE GENERATION OF STYLED VECTORS IN A GRAPHICS SYSTEM Vectors on a graphics display are styled according to a specifiable pattern of on/off segments at the same time that they are drawn on the display by integrating the styling of each pixel on the vector at the same time the location of that same pixel is determined according to Bresenham's algorithm.

公开(公告)号：CA985790A

公开(公告)日：1976-03-16

申请号：CA173525

申请日：1973-08-24

Applicant: IBM

Inventor： KIMMEL MILTON J

公开(公告)号：CA772806A

公开(公告)日：1967-11-28

申请号：CA772806D

Applicant: IBM

Inventor： KIMMEL MILTON J ,  JURSIK JAMES ,  RAZI SYED ,  WILSON NORMAN D ,  GORBATENKO GEORGE G

公开(公告)号：DE3689093T2

公开(公告)日：1994-05-05

申请号：DE3689093

申请日：1986-06-24

Applicant: IBM

Inventor： KIMMEL MILTON J

IPC: G06F7/00 ,  G06T1/20 ,  G06F15/66

公开(公告)号：DE3689093D1

公开(公告)日：1993-11-04

申请号：DE3689093

申请日：1986-06-24

Applicant: IBM

Inventor： KIMMEL MILTON J

IPC: G06F7/00 ,  G06T1/20 ,  G06F15/66

公开(公告)号：CA1258319A

公开(公告)日：1989-08-08

申请号：CA509127

申请日：1986-05-14

Applicant: IBM

Inventor： KIMMEL MILTON J

IPC: G06F7/00 ,  G06T1/20 ,  G06F9/38

Abstract: Configurable processing element groups (PEGs), made up of processing elements (PEs) and boolean combiner image switches (BC), arrayed in image processing subassemblies (CAGEs) having limited external PE connections, provide myriad image processing network choices without massive investment in memory and b us capacity. PEs have full variable connectability within the PEG, and connectability via limited bus connections to PEs in related PEGs. Image switching is implemented by the BC, which is feedback connected to PEs within the PEG. Each PEG is also directly connected to the next PEG, through its BC, in straightforward pipeline configuration. For simple jobs, the implementor configures simple networks of PEs within n PEGs. For demanding jobs, the implementor configures PEs in one PEG together with PEs from other PEGs, in a compound bus-connected network within the CAGE. For very demanding jobs, the implementor uses the PEs in the system not only as binary window processors, but also as additional switching paths, logic inverters and delay elements, setting up the image processing system most closely approaching the optimum for the job. Limitations are only bus capacity, bus con-nections and CAGE to CAGE connections. The system features host computer, video buffer, and pipeline of CAGEs, each CAGE having bit stream input an array of PEGs, and CAGE exit mechanism which provides a bit stream output in the form of X-Y coordinates of selected pels. An additional feedback loop, from BC output to BC input within the PE, significantly adds to capability with little additional oral structure.