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    3.
    发明专利
    未知

    公开(公告)号：DE1280297B

    公开(公告)日：1968-10-17

    申请号：DEJ0031307

    申请日：1966-07-13

    Applicant: IBM

    Inventor： GORBATENKO GEORGE GEROGE ,  KURSIK JAMES ,  KIMMEL MILTON JAY ,  RAZI SYED ,  WILSON NORMAN DOUGLAS

    IPC: H03M1/14 ,  G06F7/02 ,  G06F7/50 ,  G06F7/505 ,  H01H33/30 ,  H03K20060101 ,  H03M1/00 ,  H03K13/08

    Abstract: 1,101,969. A/D converters. INTERNATIONAL BUSINESS MACHINES CORPORATION. 2 Sept., 1966 [7 Oct., 1965], No. 39210/66. Heading G4H. In an analogue to digital converter of the kind in which the unknown signal is quantized to obtain the highest significant digit, and reduced by the equivalent of this digit, the remainder being multiplied by the radix and the process repeated for successive digits, the converter is adapted for inputs of either polarity by means which produce a true digital representation for the highest digit, if the input is positive, and a complementary digital representation when the input is negative so that the remainder is positive for both positive and negative inputs. The input 19, Fig. 1, is first switched by 151 to positive digitizer 300 comprising nine threshold circuits having different levels (0, 1, 2, 3, 4, 5, 6, 7 and 8 volts) and negative digitizer 400 having seven threshold circuits (with negative levels 1, 2, 3, 4, 5, 6, 7 volts). The outputs are combined in comparator Or circuits 500, are temporarily stored at 600 and are recoded at 700 into three binary scale bits, an " M " bit, signifying that the value is negative and a " P " bit indicating that the input exceeds the maximum positive range of the converter. In the case of a negative value the binary digit is the 7's complement of the input value. These bits are stored at 251 for the highest digit and at 252, 253, 254 for subsequent digits. The value stored at 251 is converted in a digital to analogue converter 201 to a voltage which is subtracted fromthe input and the difference multiplied by the radix 8 at 181. This value is then passed by switch 152 to the digitizers 300 and 400 and the process is repeated to obtain the next digit. When a binary digit is stored in any of stores 251-254 without an M or P bit the output of the DAC 201-204 is proportional to the stored digit. If an M bit is present the output is negative and has the value of the complement to 8 of the stored value. If the input is - 0À0246 volts (expressed in radix 8) the digitizer 400 produces no output and the recorder 700 produces outputs on leads 4, 2, 1 and M. This value of 7 is the complement to 7 of the value 0. When applied to the converter 201, the output produced is the complement to 8, i.e. - 1, and, when subtracted from the input value at 181, a positive difference is obtained which when multiplied by the radix 8 gives 7À532. The following digits are determined as for the positive input by successively subtracting quantized digit values and multiplying by 8 between steps. Error correcting arrangements are provided to compensate for threshold circuits in digitizers 300 and 400 which fire when they should not, or fail to fire when they should. The values stored in the stores 251- 254 and in the recoder 700 at the end of the digitizing steps are added at 800 and gated out in parallel by gates 900. The circuits are controlled by a timing circuit 100. The circuits are described in detail.

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