公开(公告)号：DE2964293D1

公开(公告)日：1983-01-20

申请号：DE2964293

申请日：1979-09-24

Applicant: IBM

Inventor： KINDSETH DOUGLAS MICHAEL ,  MITCHELL GLEN ROBERT

IPC: G06F12/02 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00

公开(公告)号：DE2963530D1

公开(公告)日：1982-10-07

申请号：DE2963530

申请日：1979-06-11

Applicant: IBM

Inventor： BEACOM THOMAS JOSEPH ,  KINDSETH DOUGLAS MICHAEL ,  MITCHELL GLEN ROBERT

IPC: G06F12/10 ,  G06F9/36 ,  G06F13/00 ,  G11C9/06

Abstract: Data processing apparatus is provided with a paging facility constrained in that the number of pages of any group of pages (defined by a specific bit pattern is a first subset of virtual address bits) in residence in the direct access data store is limited to n. The address translation apparatus included comprises two table look-up mechanisms arranged to maintain a mapping of selected virtual to real address relationships of pages in residence, the first table look-up mechanism having c/n addressable locations of n fields and the second table look-up mechanism having c single field addressable locations, when c is the maximum number of pages in residence, so that, for a filled direct access data store there is one field in each table look-up mechanism for each page in residence. Both table look-up mechanisms are addressed by the first subset of bits of a virtual address presented for translation and, in addition, the second table look-up mechanism is addressed in response to the operations of the first table look-up mechanism. Either the first or the second table look-up mechanism generates, the real page addresses appropriate to the current mapping. The first table look-up mechanism contains entries each identifying the states of a second subset of virtual address bits of pages of the associated group in residence. The second subset bits of a virtual address presented for translation are compared with all the output fields of the first table look-up mechanism using n compare circuits, outputting to the second table look-up addressing mechanism. The remaining page address bit positions of the presented virtual address are compared with the output of the second table look-up mechanism, the fields of the second table look-up mechanism containing such remaining virtual address bits appropriate to the pages in residence. If either comparator fails to detect an equality a miss is registered and the second table look-up mechanism is only exercised in relation to potential hits.