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公开(公告)号：DE2963499D1
公开(公告)日：1982-09-30
申请号：DE2963499
申请日：1979-09-24
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , SOLTIS FRANK GERALD , HOFFMAN ROY LOUIS
Abstract: Virtual addressing apparatus for implementing a large virtual address in a computer system having narrow data paths, ALU, and local storage register arrays without requiring multiple passes. The virtual addressing apparatus stores the segment portion of a virtual address in a segment register and the offset portion of the virtual address in an offset register. To form a new virtual address, a new offset value is obtained by adding the displacement value given by the instruction in the instruction buffer register to the offset value stored in the offset register. The segment portion of the virtual address does not participate in the arithmetic operation for forming the new virtual address. The segment and offset portions are concatenated to form the new virtual address which is then translated to a main store address. Overflow detection circuitry in the ALU detects if an overflow out of the offset occurs as a result of the ALU operation for obtaining the new offset value. If an overflow is detected during the calculation of the new offset value, translation of the virtual address is subsequently aborted.
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公开(公告)号：DE2962460D1
公开(公告)日：1982-05-19
申请号：DE2962460
申请日：1979-09-24
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , HOUDEK MERLE EDWARD
Abstract: The present invention discloses an apparatus for the efficient translation of virtual addresses to main storage addresses by means of a hash index table which contains main storage addresses. Hash generator apparatus is provided for generating a uniform distribution of hash index table entry addresses from a non-uniform distribution of virtual addresses in a data processing system, where the size of the hash index table is variable and is based on the size of main storage. A field of bits within the virtual address corresponding to the page identification bits are reversed in order and aligned with two groups of bits from a field of bits within the virtual address corresponding to object identification bits, and the three groups of bits are applied to an EXCLUSIVE-OR circuit. The alignment of the three groups of bits and the size of the hash index table entry addresses generated by the present invention are based on the size of the hash index table.
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公开(公告)号：DE2965742D1
公开(公告)日：1983-07-28
申请号：DE2965742
申请日：1979-09-24
Applicant: IBM
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公开(公告)号：IT7926082D0
公开(公告)日：1979-09-28
申请号：IT2608279
申请日：1979-09-28
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , HOUDEK MERLE EDWARD
Abstract: The present invention discloses an apparatus for the efficient translation of virtual addresses to main storage addresses by means of a hash index table which contains main storage addresses. Hash generator apparatus is provided for generating a uniform distribution of hash index table entry addresses from a non-uniform distribution of virtual addresses in a data processing system, where the size of the hash index table is variable and is based on the size of main storage. A field of bits within the virtual address corresponding to the page identification bits are reversed in order and aligned with two groups of bits from a field of bits within the virtual address corresponding to object identification bits, and the three groups of bits are applied to an EXCLUSIVE-OR circuit. The alignment of the three groups of bits and the size of the hash index table entry addresses generated by the present invention are based on the size of the hash index table.
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公开(公告)号：IT7926081D0
公开(公告)日：1979-09-28
申请号：IT2608179
申请日：1979-09-28
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , SOLTIS FRANK GERALD , HOFFMAN ROY LOUIS
Abstract: Virtual addressing apparatus for implementing a large virtual address in a computer system having narrow data paths, ALU, and local storage register arrays without requiring multiple passes. The virtual addressing apparatus stores the segment portion of a virtual address in a segment register and the offset portion of the virtual address in an offset register. To form a new virtual address, a new offset value is obtained by adding the displacement value given by the instruction in the instruction buffer register to the offset value stored in the offset register. The segment portion of the virtual address does not participate in the arithmetic operation for forming the new virtual address. The segment and offset portions are concatenated to form the new virtual address which is then translated to a main store address. Overflow detection circuitry in the ALU detects if an overflow out of the offset occurs as a result of the ALU operation for obtaining the new offset value. If an overflow is detected during the calculation of the new offset value, translation of the virtual address is subsequently aborted.
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Patent Agency Ranking
公开(公告)号：IT1165345B
公开(公告)日：1987-04-22
申请号：IT2608079
申请日：1979-09-28
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , KEMPKE WILLIAM GEORGE , JONES EUGENE REESE , HOUDEK MERLE EDWARD , RANWEILER JAMES GREGORY
Abstract: Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction. Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.
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公开(公告)号：IT1163717B
公开(公告)日：1987-04-08
申请号：IT2608179
申请日：1979-09-28
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , SOLTIS FRANK GERALD , HOFFMAN ROY LOUIS
Abstract: Virtual addressing apparatus for implementing a large virtual address in a computer system having narrow data paths, ALU, and local storage register arrays without requiring multiple passes. The virtual addressing apparatus stores the segment portion of a virtual address in a segment register and the offset portion of the virtual address in an offset register. To form a new virtual address, a new offset value is obtained by adding the displacement value given by the instruction in the instruction buffer register to the offset value stored in the offset register. The segment portion of the virtual address does not participate in the arithmetic operation for forming the new virtual address. The segment and offset portions are concatenated to form the new virtual address which is then translated to a main store address. Overflow detection circuitry in the ALU detects if an overflow out of the offset occurs as a result of the ALU operation for obtaining the new offset value. If an overflow is detected during the calculation of the new offset value, translation of the virtual address is subsequently aborted.
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公开(公告)号：IT1162587B
公开(公告)日：1987-04-01
申请号：IT2607979
申请日：1979-09-28
Applicant: IBM
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公开(公告)号：IT1165346B
公开(公告)日：1987-04-22
申请号：IT2608279
申请日：1979-09-28
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , HOUDEK MERLE EDWARD
Abstract: The present invention discloses an apparatus for the efficient translation of virtual addresses to main storage addresses by means of a hash index table which contains main storage addresses. Hash generator apparatus is provided for generating a uniform distribution of hash index table entry addresses from a non-uniform distribution of virtual addresses in a data processing system, where the size of the hash index table is variable and is based on the size of main storage. A field of bits within the virtual address corresponding to the page identification bits are reversed in order and aligned with two groups of bits from a field of bits within the virtual address corresponding to object identification bits, and the three groups of bits are applied to an EXCLUSIVE-OR circuit. The alignment of the three groups of bits and the size of the hash index table entry addresses generated by the present invention are based on the size of the hash index table.
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公开(公告)号：DE2963530D1
公开(公告)日：1982-10-07
申请号：DE2963530
申请日：1979-06-11
Applicant: IBM
Inventor： BEACOM THOMAS JOSEPH , KINDSETH DOUGLAS MICHAEL , MITCHELL GLEN ROBERT
Abstract: Data processing apparatus is provided with a paging facility constrained in that the number of pages of any group of pages (defined by a specific bit pattern is a first subset of virtual address bits) in residence in the direct access data store is limited to n. The address translation apparatus included comprises two table look-up mechanisms arranged to maintain a mapping of selected virtual to real address relationships of pages in residence, the first table look-up mechanism having c/n addressable locations of n fields and the second table look-up mechanism having c single field addressable locations, when c is the maximum number of pages in residence, so that, for a filled direct access data store there is one field in each table look-up mechanism for each page in residence. Both table look-up mechanisms are addressed by the first subset of bits of a virtual address presented for translation and, in addition, the second table look-up mechanism is addressed in response to the operations of the first table look-up mechanism. Either the first or the second table look-up mechanism generates, the real page addresses appropriate to the current mapping. The first table look-up mechanism contains entries each identifying the states of a second subset of virtual address bits of pages of the associated group in residence. The second subset bits of a virtual address presented for translation are compared with all the output fields of the first table look-up mechanism using n compare circuits, outputting to the second table look-up addressing mechanism. The remaining page address bit positions of the presented virtual address are compared with the output of the second table look-up mechanism, the fields of the second table look-up mechanism containing such remaining virtual address bits appropriate to the pages in residence. If either comparator fails to detect an equality a miss is registered and the second table look-up mechanism is only exercised in relation to potential hits.
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