公开(公告)号：EP1463118A4

公开(公告)日：2008-07-02

申请号：EP02777998

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  SUNAGA TOSHIO ,  MIYATAKE HISATADA

IPC: G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/10 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

CPC classification number: H01L27/224 ,  H01L21/84

Abstract: An MRAM memory cell structure for preventing a parasitic transistor from generating. A diode is used as an MRAM memory cell switching element to form an n-type semiconductor layer (25) and a p-type semiconductor layer (29) that constitute a diode on the surface semiconductor layer of an SOI substrate. The n-type semiconductor layer (25) and the p-type semiconductor layer (29) are disposed in a lateral direction and separated by an isolation region (5) for electrically isolating from other elements or the substrate.

公开(公告)号：CA2462940A1

公开(公告)日：2003-05-08

申请号：CA2462940

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  SUNAGA TOSHIO ,  MIYATAKE HISATADA

IPC: G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/10 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

Abstract: An MRAM memory cell structure for preventing a parasitic transistor from generating. A diode is used as an MRAM memory cell switching element to form an n-type semiconductor layer (25) and a p-type semiconductor layer (29) tha t constitute a diode on the surface semiconductor layer of an SOI substrate. T he n-type semiconductor layer (25) and the p-type semiconductor layer (29) are disposed in a lateral direction and separated by an isolation region (5) for electrically isolating from other elements or the substrate.

公开(公告)号：CA2462940C

公开(公告)日：2009-11-17

申请号：CA2462940

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  MIYATAKE HISATADA ,  SUNAGA TOSHIO

IPC: H01L27/10 ,  G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

Abstract: Provided is an MRAM memory cell structure capable of preventing generation o f parasitic transistors. Diodes are adopted as switching elements of an MRAM memory cell. An n-type semiconductor layer and a p-type semiconductor layer, which collectively constitute a diod e, are formed on a surface semiconductor layer of an SOI substrate. The n-type semiconductor layer and the p-type semiconductor layer are disposed in a lateral direction and isolated by an isolation region, whereby the diode is isolated electrically from other elements and from the substrat e.