公开(公告)号：EP1626412A4

公开(公告)日：2006-08-30

申请号：EP04727148

申请日：2004-04-13

Applicant: IBM

Inventor： SUNAGA TOSHIO ,  HOSOKAWA KOHJI ,  MIYATAKE HISATADA

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: It is possible to realize a DRAM of a simple circuit structure capable of effectively reducing the refresh current by setting the refresh cycle by a small step. A memory array is divided into 64 sub-arrays, each of which is further divided into eight blocks. A refresh cycle control circuit (RCCC) includes: a fuse circuit (FC0) for setting 1 or 1/2 division ratio; a divider (FD0) for dividing a pre-decode signal(ZLI0) with the division ratio which has been set; fuse circuits (FC1 to FC8) for setting 1 or 1/4 division ratio; and dividers (FD1 to FD8) for dividing pre-decode signals (ZLI1 to ZLI8) with the set division ratio. The refresh cycle control circuit (RCCC) can set the 64 or 128 ms refresh cycle for the 64 sub-arrays and the 64 or 256 ms refresh cycle for the 512 blocks.

Abstract translation: 可以通过以较小的步长设置刷新周期来实现能够有效地降低刷新电流的简单电路结构的DRAM。 存储器阵列被分成64个子阵列，每个阵列又被分成8个块。 刷新周期控制电路（RCCC）包括：用于设定1或1/2分频比的熔丝电路（FC0） 分频器（FD0），用于以已经设定的分频比对预解码信号（ZLI0）进行分频; 用于设置1或1/4分频比的熔丝电路（FC1至FC8）; 和分频器（FD1到FD8），用于以设定的分频比分割预解码信号（ZLI1到ZLI8）。 刷新周期控制电路（RCCC）可以为64个子阵列设置64或128 ms的刷新周期，并为512个块设置64或256 ms的刷新周期。

公开(公告)号：EP1463118A4

公开(公告)日：2008-07-02

申请号：EP02777998

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  SUNAGA TOSHIO ,  MIYATAKE HISATADA

IPC: G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/10 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

CPC classification number: H01L27/224 ,  H01L21/84

Abstract: An MRAM memory cell structure for preventing a parasitic transistor from generating. A diode is used as an MRAM memory cell switching element to form an n-type semiconductor layer (25) and a p-type semiconductor layer (29) that constitute a diode on the surface semiconductor layer of an SOI substrate. The n-type semiconductor layer (25) and the p-type semiconductor layer (29) are disposed in a lateral direction and separated by an isolation region (5) for electrically isolating from other elements or the substrate.

公开(公告)号：EP1968071A4

公开(公告)日：2009-06-03

申请号：EP06843204

申请日：2006-12-25

Applicant: IBM

Inventor： SUNAGA TOSHIO

IPC: G11C11/4074

CPC classification number: G11C11/4074 ,  G11C5/145 ,  G11C2207/2227

Abstract: [PROBLEMS] To provide a memory system capable of reducing a large current consumption during an active state and a stand-by state by increasing the efficiency of a voltage generation circuit in a DRAM or the like having a charge pump circuit or the like and a method for reducing the current. [MEANS FOR SOLVING PROBLEMS] A memory system includes a high voltage supply boost circuit for supplying pre-charged electric charge to an access control circuit in response to an access start request for a memory cell array and driving the access control circuit from a low voltage for the memory access to a high voltage. Moreover, the memory system further includes a low voltage supply boost circuit for absorbing an excessive electric charge generated when the access control circuit is switched from the high voltage to the low voltage in response to the access end request to the memory cell array.

公开(公告)号：EP1912222A4

公开(公告)日：2009-05-13

申请号：EP06781647

申请日：2006-07-26

Applicant: IBM

Inventor： SUNAGA TOSHIO ,  FUJITA NORIO

IPC: G11C11/401 ,  G11C11/407

CPC classification number: G11C7/22 ,  G11C8/10 ,  G11C11/4076 ,  G11C2207/2218

Abstract: [PROBLEMS] To shorten an access cycle time and improve data rate for data input/output (I/O), in a memory to which single-write can be performed. [MEANS FOR SOLVING PROBLEMS] The memory is provided with a latch circuit for latching a read address and a write address inputted from an address input; an address selecting circuit for selecting either the read address or the write address latched by the latch circuit as an access address; a read latch circuit for latching read data read by a memory cell array; a write latch circuit for latching write data inputted from the data input/output; and a control circuit for controlling the access address selected by the address selecting circuit by receiving a command inputted from a command input. Furthermore, the memory is provided with a control circuit for controlling timing for writing in a memory cell wherein the write data latched by the write latch circuit is activated.

公开(公告)号：CA2462940A1

公开(公告)日：2003-05-08

申请号：CA2462940

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  SUNAGA TOSHIO ,  MIYATAKE HISATADA

IPC: G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/10 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

Abstract: An MRAM memory cell structure for preventing a parasitic transistor from generating. A diode is used as an MRAM memory cell switching element to form an n-type semiconductor layer (25) and a p-type semiconductor layer (29) tha t constitute a diode on the surface semiconductor layer of an SOI substrate. T he n-type semiconductor layer (25) and the p-type semiconductor layer (29) are disposed in a lateral direction and separated by an isolation region (5) for electrically isolating from other elements or the substrate.

公开(公告)号：CA2462940C

公开(公告)日：2009-11-17

申请号：CA2462940

申请日：2002-10-29

Applicant: IBM

Inventor： KIRAMURA KOHJI ,  MIYATAKE HISATADA ,  SUNAGA TOSHIO

IPC: H01L27/10 ,  G11C11/15 ,  G11C11/36 ,  H01L21/336 ,  H01L21/84 ,  H01L27/105 ,  H01L27/146 ,  H01L27/22

Abstract: Provided is an MRAM memory cell structure capable of preventing generation o f parasitic transistors. Diodes are adopted as switching elements of an MRAM memory cell. An n-type semiconductor layer and a p-type semiconductor layer, which collectively constitute a diod e, are formed on a surface semiconductor layer of an SOI substrate. The n-type semiconductor layer and the p-type semiconductor layer are disposed in a lateral direction and isolated by an isolation region, whereby the diode is isolated electrically from other elements and from the substrat e.

公开(公告)号：SG77144A1

公开(公告)日：2000-12-19

申请号：SG1997002951

申请日：1997-08-15

Applicant: IBM

Inventor： WATANABE SHINPEI ,  SUNAGA TOSHIO

IPC: G06F12/00 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096

Abstract: A DRAM system that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order so that a seamless operation is assured not only for reading but also for writing. A prefetch mechanism is used for reading and writing data to a separate memory array at an early stage, so that the activation and precharge operation, which must be performed before reading the next set of data from the memory array, does not affect nor cause any deterioration of access speed. The amount of data prefetched is twice as much as that fetched in the period represented by an array time constant so that in a single bank structure a seamless operation can be performed both for reading and for writing, even when row accesses are performed.

公开(公告)号：AT521971T

公开(公告)日：2011-09-15

申请号：AT06843204

申请日：2006-12-25

Applicant: IBM

Inventor： SUNAGA TOSHIO

IPC: G11C11/4074

公开(公告)号：DE602004022157D1

公开(公告)日：2009-09-03

申请号：DE602004022157

申请日：2004-04-13

Applicant: IBM

Inventor： SUNAGA TOSHIO ,  HOSOKAWA KOHJI ,  MIYATAKE HISATADA

IPC: G11C11/406

Abstract: To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by detailedly setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.

公开(公告)号：AT437439T

公开(公告)日：2009-08-15

申请号：AT04727148

申请日：2004-04-13

Applicant: IBM

Inventor： SUNAGA TOSHIO ,  HOSOKAWA KOHJI ,  MIYATAKE HISATADA

IPC: G11C11/406

Abstract: To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by detailedly setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.