公开(公告)号：JP2003031925A

公开(公告)日：2003-01-31

申请号：JP2002136832

申请日：2002-05-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CLOTHIER RONALD ,  KNIGHT JEFFREY ALAN ,  SEBESTA ROBERT DAVID

IPC: H05K1/11 ,  C25D7/12 ,  H05K1/02 ,  H05K1/18 ,  H05K3/18 ,  H05K3/20 ,  H05K3/22 ,  H05K3/46

CPC classification number: C25D7/123 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K3/205 ,  Y10T428/12361 ,  Y10T428/12438 ,  Y10T428/12569 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a structure having a high-density embedded same plane circuit feature. SOLUTION: This structure is equipped with a support foil, an electrical conductive layer formed on the one main surface of the support foil, a dielectric layer which is located on the electrical conductive layer and provided with a circuit feature, and a metal conductive circuit located in the circuit feature. The metal conductive circuit and the dielectric layer are substantially located on the same plane, and the metal conductive circuit is surrounded by the dielectric layer. The embedded same planar circuit feature is formed through a process of providing a support foil with an electrical conductive layer and of coating the electrical conductive layer with a dielectric material. A circuit feature is formed on a dielectric material, and conductive metal plating is carried out, so as to fill up the circuit feature.

Abstract translation: 要解决的问题：提供具有高密度嵌入式同平面电路特征的结构。 解决方案：该结构配备有支撑箔，形成在支撑箔的一个主表面上的导电层，位于导电层上并具有电路特征的电介质层和位于 在电路特性中。 金属导电电路和电介质层基本上位于同一平面上，金属导电电路被电介质层包围。 嵌入的相同的平面电路特征是通过提供具有导电层的支撑箔和用介电材料涂覆导电层的过程形成的。 在电介质材料上形成电路特征，进行导电金属电镀，以填满电路特征。

公开(公告)号：WO9625763A3

公开(公告)日：1996-11-07

申请号：PCT/EP9600180

申请日：1996-01-17

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

CPC classification number: H05K1/021 ,  H01L23/145 ,  H01L23/3677 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K1/182 ,  H05K3/0061 ,  H05K2201/09127 ,  H05K2201/09981 ,  H05K2203/049 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A chip carrier (10) for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer (110), having plated photo-vias (120), to electrically interconnect two (or more) layers (80, 130) of fan-out circuitry. This chip carrier further employs a single-tiered cavity (140) to contain a chip (150), rather than a multi-tiered cavity,as is conventional. Moreover, this chip carrier includes thermal via holes (170) and/or a metallic layer (230), directly beneath the chip (150), to enhance heat dissipation.

Abstract translation: 公开了一种用于引线接合型芯片的芯片载体。 该芯片载体采用有机电介质材料，而不是常规的陶瓷材料。 该芯片载体还采用至少一个具有电镀光通孔的有机光可成像介质层，以电连接两个（或多个）扇出电路层。 该芯片载体还采用单层空腔来容纳芯片而不是多层腔，如常规的那样。 此外，该芯片载体包括直接在芯片下方的热通孔和/或金属层，以增强散热。

公开(公告)号：CZ286385B6

公开(公告)日：2000-03-15

申请号：CZ225697

申请日：1996-01-17

Applicant: IBM ,  IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: The invented chip carrier (10) for a chip with wire connections employs rather organic dielectric materials than the ceramic ones, which are commonly used. The chip carrier also employs at least one organic dielectric layer (110) that may be displayed by light and having plated light routes (120) for electric interconnection of two (or more) layers of output branching circuits (120). This chip carrier (10) further contains rather a simple cavity (140 for placing therein the chip (150) than a complex cavity that is commonly used. In addition, this chip carrier (10) contains through holes (170) and/or a metallic layer (230) situated immediately beneath the chip (150) and serving for enhancing thermal dissipation.

公开(公告)号：AT187014T

公开(公告)日：1999-12-15

申请号：AT96901290

申请日：1996-01-17

Applicant: IBM ,  IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

公开(公告)号：SG34493A1

公开(公告)日：1996-12-06

申请号：SG1996000133

申请日：1996-01-10

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/14 ,  H01L23/367 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02 ,  H01L23/26 ,  H05K1/00

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

公开(公告)号：HU9702316A2

公开(公告)日：1998-03-02

申请号：HU9702316

申请日：1996-01-17

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PARTICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

公开(公告)号：CA2164901A1

公开(公告)日：1996-08-16

申请号：CA2164901

申请日：1995-12-11

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02 ,  H01L23/50

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multitiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and / or a metallic layer, directly beneath the chip, to enhance heat dissipation.

公开(公告)号：MY140232A

公开(公告)日：2009-12-31

申请号：MYPI9600367

申请日：1996-01-31

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H01L23/367 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: A CHIP CARRIER (10) FOR WIRE BOND-TYPE CHIPS IS DISLCOSED. THIS CHIP CARRIER EMPLOYS ORGANIC DIELECTRIC MATERIALS, RATHER THAN CERAMIC MATERIALS, AS IS CONVENTIONAL. THIS CHIP CARRIER ALSO EMPLOYES AT LEAST ONE ORGANIC, PHOTOIMAGEABLE DIELECTRIC LAYER (110), HAVING PLATED PHOTO-VIAS (120), TO ELECTRICALLY INTERCONNECT TWO (OR MORE) LAYERS (80, 130) OF FAN-OUT CIRCUITRY. THIS CHIP CARRIER FURTHER EMPLOYS A SINGLE-TIERED CAVITY (140) TO CONTAIN A CHIP (150), RATHER THAN A MUTLI-TIERED CAVITY, AS IS CONVENTIONAL. MOREOVER, THIS CHIP CARRIER INCLUDES THERMAL VIA HOLES (170) AND/OR A METALLIC LAYER (230), DIRECTLY BENEATH THE CHIP (150), TO ENHANCE HEAT DISSIPATION.

公开(公告)号：ES2139330T3

公开(公告)日：2000-02-01

申请号：ES96901290

申请日：1996-01-17

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

公开(公告)号：HU216982B

公开(公告)日：1999-10-28

申请号：HU9702316

申请日：1996-01-17

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PARTICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.