公开(公告)号：WO9625763A3

公开(公告)日：1996-11-07

申请号：PCT/EP9600180

申请日：1996-01-17

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

CPC classification number: H05K1/021 ,  H01L23/145 ,  H01L23/3677 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K1/182 ,  H05K3/0061 ,  H05K2201/09127 ,  H05K2201/09981 ,  H05K2203/049 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A chip carrier (10) for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer (110), having plated photo-vias (120), to electrically interconnect two (or more) layers (80, 130) of fan-out circuitry. This chip carrier further employs a single-tiered cavity (140) to contain a chip (150), rather than a multi-tiered cavity,as is conventional. Moreover, this chip carrier includes thermal via holes (170) and/or a metallic layer (230), directly beneath the chip (150), to enhance heat dissipation.

Abstract translation: 公开了一种用于引线接合型芯片的芯片载体。 该芯片载体采用有机电介质材料，而不是常规的陶瓷材料。 该芯片载体还采用至少一个具有电镀光通孔的有机光可成像介质层，以电连接两个（或多个）扇出电路层。 该芯片载体还采用单层空腔来容纳芯片而不是多层腔，如常规的那样。 此外，该芯片载体包括直接在芯片下方的热通孔和/或金属层，以增强散热。

公开(公告)号：AT187014T

公开(公告)日：1999-12-15

申请号：AT96901290

申请日：1996-01-17

Applicant: IBM ,  IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

公开(公告)号：CZ286385B6

公开(公告)日：2000-03-15

申请号：CZ225697

申请日：1996-01-17

Applicant: IBM ,  IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: The invented chip carrier (10) for a chip with wire connections employs rather organic dielectric materials than the ceramic ones, which are commonly used. The chip carrier also employs at least one organic dielectric layer (110) that may be displayed by light and having plated light routes (120) for electric interconnection of two (or more) layers of output branching circuits (120). This chip carrier (10) further contains rather a simple cavity (140 for placing therein the chip (150) than a complex cavity that is commonly used. In addition, this chip carrier (10) contains through holes (170) and/or a metallic layer (230) situated immediately beneath the chip (150) and serving for enhancing thermal dissipation.

公开(公告)号：SG34493A1

公开(公告)日：1996-12-06

申请号：SG1996000133

申请日：1996-01-10

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/14 ,  H01L23/367 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02 ,  H01L23/26 ,  H05K1/00

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

公开(公告)号：SG44058A1

公开(公告)日：1997-11-14

申请号：SG1996010841

申请日：1996-10-14

Applicant: IBM

Inventor： BHATT ANILKUMAR CHINUPRASAD ,  BHATT ASHWINKUMAR CHINUPRASAD ,  DAY ROBERT JEFFERY ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFERY ALAN ,  MALEK RICHARD WILLIAM ,  MARKOVICH VOYA RISTA

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/42 ,  C25D5/02 ,  H05K3/02

Abstract: A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e.g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.

公开(公告)号：CA2164901A1

公开(公告)日：1996-08-16

申请号：CA2164901

申请日：1995-12-11

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02 ,  H01L23/50

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multitiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and / or a metallic layer, directly beneath the chip, to enhance heat dissipation.

公开(公告)号：PL321595A1

公开(公告)日：1997-12-08

申请号：PL32159596

申请日：1996-01-17

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/14 ,  H01L23/12 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

公开(公告)号：MY140232A

公开(公告)日：2009-12-31

申请号：MYPI9600367

申请日：1996-01-31

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H01L23/367 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: A CHIP CARRIER (10) FOR WIRE BOND-TYPE CHIPS IS DISLCOSED. THIS CHIP CARRIER EMPLOYS ORGANIC DIELECTRIC MATERIALS, RATHER THAN CERAMIC MATERIALS, AS IS CONVENTIONAL. THIS CHIP CARRIER ALSO EMPLOYES AT LEAST ONE ORGANIC, PHOTOIMAGEABLE DIELECTRIC LAYER (110), HAVING PLATED PHOTO-VIAS (120), TO ELECTRICALLY INTERCONNECT TWO (OR MORE) LAYERS (80, 130) OF FAN-OUT CIRCUITRY. THIS CHIP CARRIER FURTHER EMPLOYS A SINGLE-TIERED CAVITY (140) TO CONTAIN A CHIP (150), RATHER THAN A MUTLI-TIERED CAVITY, AS IS CONVENTIONAL. MOREOVER, THIS CHIP CARRIER INCLUDES THERMAL VIA HOLES (170) AND/OR A METALLIC LAYER (230), DIRECTLY BENEATH THE CHIP (150), TO ENHANCE HEAT DISSIPATION.

公开(公告)号：ES2139330T3

公开(公告)日：2000-02-01

申请号：ES96901290

申请日：1996-01-17

Applicant: IBM

Inventor： BHATT ASHWINKUMAR CHINUPRASAD ,  DESAI SUBAHU DHIRUBHAI ,  DUFFY THOMAS PATRICK ,  KNIGHT JEFFREY ALAN

IPC: H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

Abstract: A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.