公开(公告)号：JPH1012819A

公开(公告)日：1998-01-16

申请号：JP7316397

申请日：1997-03-26

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  HARAME DAVID LOUIS ,  HUECKEL GARY ROBERT ,  KOCIS JOSEPH THOMAS ,  NGOC DOMINIQUE NGUYEN ,  STEIN KENNETH JAY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prevent high leak current and shot-circuiting, by forming a capaci tor between interconnection wiring layers of a semiconductor chip having a clean interface free from residue produced by treatment. SOLUTION: A capacitor 20 is formed between a mutual connection wiring 12 of a first level and an interconnection wiring layer 11 of a second level. A via 36 electrically connects the capacitor 20 with the mutual connection wiring 11 of the second level. The interconnection wiring 12 of the first level is used as a lower electrode of the capacitor 20, i.e., a base electrode, and connected with a lower via 30. The via 30 is formed in dielectric 22 and mutually connected with a lower conducting region. The dielectrics layer 22 and the upper surface of the via 30 are polished, and an insulating region and the conducting region form the same surface 31. The capacitor 20 is constituted of e.g. the interconnection wiring 12 of the first level, a dielectrics layer 14 and a layer of an upper electrode or a facing electrode 16. The upper electrode 16 is so formed that its peripheral edge is positioned inside the peripheral edge of the dielectrics layer 14.

公开(公告)号：DE69712968D1

公开(公告)日：2002-07-11

申请号：DE69712968

申请日：1997-03-17

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  HARAME DAVID LOUIS ,  HUECKEL GARY ROBERT ,  KOCIS JOSEPH THOMAS ,  NGOC DOMINIQUE NGUYEN ,  STEIN KENNETH JAY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92 ,  H01L21/3205 ,  H01L23/64

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring (12,11) separated by a first dielectric (35), a capacitor (20) formed by a second dielectric (14), a bottom electrode of the lower interconnection wiring (12) or a via and a top electrode of the upper interconnection wiring or a separate metal layer (17,18,19). The system overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

公开(公告)号：DE69712968T2

公开(公告)日：2003-01-16

申请号：DE69712968

申请日：1997-03-17

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  HARAME DAVID LOUIS ,  HUECKEL GARY ROBERT ,  KOCIS JOSEPH THOMAS ,  NGOC DOMINIQUE NGUYEN ,  STEIN KENNETH JAY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92 ,  H01L21/3205 ,  H01L23/64

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring (12,11) separated by a first dielectric (35), a capacitor (20) formed by a second dielectric (14), a bottom electrode of the lower interconnection wiring (12) or a via and a top electrode of the upper interconnection wiring or a separate metal layer (17,18,19). The system overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.