公开(公告)号：WO2007057472A3

公开(公告)日：2008-01-17

申请号：PCT/EP2006068721

申请日：2006-11-21

Applicant: IBM ,  IBM UK ,  DEVRIES KENNETH LAWRENCE ,  GRECO NANCY ANNE ,  PRESTON JOAN ,  RUNYON STEPHEN LARRY

Inventor： DEVRIES KENNETH LAWRENCE ,  GRECO NANCY ANNE ,  PRESTON JOAN ,  RUNYON STEPHEN LARRY

IPC: H01L23/522 ,  H01L21/74 ,  H01L23/528 ,  H01L23/60

CPC classification number: H01L23/5226 ,  H01L21/743 ,  H01L23/5286 ,  H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Abstract translation: 在SOI衬底上集成电路中设计电荷耗散结构的方法和结构及方法。 第一结构包括围绕集成电路芯片的周边的电荷耗散环以及物理和电连接到电荷消耗基座的一个或多个电荷消耗基座。 SOI衬底的硅层和体硅层通过保护环和电荷消耗基座连接。 集成电路芯片的地面配电网连接到一个或多个电荷消耗基座的最上面的线段。 第二种结构，用额外的电荷消耗基座元件代替电荷消除保护环。

公开(公告)号：JPH1012819A

公开(公告)日：1998-01-16

申请号：JP7316397

申请日：1997-03-26

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  HARAME DAVID LOUIS ,  HUECKEL GARY ROBERT ,  KOCIS JOSEPH THOMAS ,  NGOC DOMINIQUE NGUYEN ,  STEIN KENNETH JAY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prevent high leak current and shot-circuiting, by forming a capaci tor between interconnection wiring layers of a semiconductor chip having a clean interface free from residue produced by treatment. SOLUTION: A capacitor 20 is formed between a mutual connection wiring 12 of a first level and an interconnection wiring layer 11 of a second level. A via 36 electrically connects the capacitor 20 with the mutual connection wiring 11 of the second level. The interconnection wiring 12 of the first level is used as a lower electrode of the capacitor 20, i.e., a base electrode, and connected with a lower via 30. The via 30 is formed in dielectric 22 and mutually connected with a lower conducting region. The dielectrics layer 22 and the upper surface of the via 30 are polished, and an insulating region and the conducting region form the same surface 31. The capacitor 20 is constituted of e.g. the interconnection wiring 12 of the first level, a dielectrics layer 14 and a layer of an upper electrode or a facing electrode 16. The upper electrode 16 is so formed that its peripheral edge is positioned inside the peripheral edge of the dielectrics layer 14.

公开(公告)号：JPH10209071A

公开(公告)日：1998-08-07

申请号：JP154298

申请日：1998-01-07

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  GRECO STEPHEN EDWARD ,  WAGNER TINA JANE

IPC: H01L21/28 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To obtain perfect optical resolution of holes and bars by using a conventional manufacturing equipment, by forming a plurality of second aperture parts which correspond to a plurality of second patterned features and stretch through a first and a second layers, in the second layer, filling the aperture parts. SOLUTION: A first layer is formed on a semiconductor substrate 4, and only a plurality of first features having a first feature size are patterned on the first layer. Parts of the first layer which correspond to the patterned first features are eliminated, and a plurality of aperture parts are formed in the first layer and filled. A second layer is formed on the first layer and the filled aperture parts, a plurality of second features having a second feature size are patterned on the second layer, and parts of the first and the second layer which correspond to the patterned second features are eliminated. As a result, a plurality of second aperture parts which correspond to a plurality of the second patterned features and stretch through the first and the second layers are formed in the second layer and filled.

公开(公告)号：DE69712968D1

公开(公告)日：2002-07-11

申请号：DE69712968

申请日：1997-03-17

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  HARAME DAVID LOUIS ,  HUECKEL GARY ROBERT ,  KOCIS JOSEPH THOMAS ,  NGOC DOMINIQUE NGUYEN ,  STEIN KENNETH JAY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92 ,  H01L21/3205 ,  H01L23/64

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring (12,11) separated by a first dielectric (35), a capacitor (20) formed by a second dielectric (14), a bottom electrode of the lower interconnection wiring (12) or a via and a top electrode of the upper interconnection wiring or a separate metal layer (17,18,19). The system overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

公开(公告)号：DE69738705D1

公开(公告)日：2008-07-03

申请号：DE69738705

申请日：1997-12-19

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  GRECO STEPHEN EDWARD ,  WAGNER TINA JANE

IPC: H01L21/28 ,  H01L21/768

Abstract: A method of fabricating semiconductor structures, particularly contact structures, forms features of differing sizes at different points in the semiconductor process, so as to enhance lithographic resolution.

公开(公告)号：DE3779043D1

公开(公告)日：1992-06-17

申请号：DE3779043

申请日：1987-08-25

Applicant: IBM

Inventor： BROOKS GARTH ALWYN ,  GRECO NANCY ANNE

IPC: H01L21/302 ,  G03F7/16 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/00

Abstract: Disclosed is a process for forming a planarized multilevel chip wiring structure. Starting from a substrate (30) having thereon at least a metal stud (32) serving as vertical wiring between two levels of metallization, a quartz layer (36) is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist (42) is applied. The photoresist is converted by silylation process into an organosilicate (46) having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting the resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazane, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.

公开(公告)号：AU2020385264A1

公开(公告)日：2022-04-28

申请号：AU2020385264

申请日：2020-11-10

Applicant: IBM

Inventor： DANG XUAN-HONG ,  SHAH SYED YOUSAF ,  ZERFOS PETROS ,  GRECO NANCY ANNE

IPC: G06N3/08

Abstract: Embodiments relate to a system, program product, and method for employing deep learning techniques to fused data across modalities. A multi-modal data set is received, including a first data set having a first modality and a second data set having a second modality, with the second modality being different from the first modality. The first and second data sets are processed, including encoding the first data set into one or more first vectors, and encoding the second data set into one or more second vectors. The processed multi-modal data set is analyzed, and the encoded features from the first and second modalities are iteratively and asynchronously fused. The fused modalities include combined vectors from the first and second data sets representing correlated temporal behavior. The fused vectors are then returned as output data.

公开(公告)号：DE69712968T2

公开(公告)日：2003-01-16

申请号：DE69712968

申请日：1997-03-17

Applicant: IBM

Inventor： GRECO NANCY ANNE ,  HARAME DAVID LOUIS ,  HUECKEL GARY ROBERT ,  KOCIS JOSEPH THOMAS ,  NGOC DOMINIQUE NGUYEN ,  STEIN KENNETH JAY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92 ,  H01L21/3205 ,  H01L23/64

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring (12,11) separated by a first dielectric (35), a capacitor (20) formed by a second dielectric (14), a bottom electrode of the lower interconnection wiring (12) or a via and a top electrode of the upper interconnection wiring or a separate metal layer (17,18,19). The system overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

公开(公告)号：AU594518B2

公开(公告)日：1990-03-08

申请号：AU8013187

申请日：1987-10-26

Applicant: IBM

Inventor： BROOKS GARTH ALWYN ,  GRECO NANCY ANNE

IPC: H01L21/302 ,  G03F7/16 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/461 ,  H01L21/64

Abstract: Disclosed is a process for forming a planarized multilevel chip wiring structure. Starting from a substrate (30) having thereon at least a metal stud (32) serving as vertical wiring between two levels of metallization, a quartz layer (36) is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist (42) is applied. The photoresist is converted by silylation process into an organosilicate (46) having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting the resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazane, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.

公开(公告)号：AU8013187A

公开(公告)日：1988-05-05

申请号：AU8013187

申请日：1987-10-26

Applicant: IBM

Inventor： BROOKS GARTH ALWYN ,  GRECO NANCY ANNE

IPC: H01L21/302 ,  G03F7/16 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/461 ,  H01L21/64

Abstract: Disclosed is a process for forming a planarized multilevel chip wiring structure. Starting from a substrate (30) having thereon at least a metal stud (32) serving as vertical wiring between two levels of metallization, a quartz layer (36) is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist (42) is applied. The photoresist is converted by silylation process into an organosilicate (46) having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting the resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazane, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.